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| a p ril 2008 rev. 5 1/164 st72324jx st72324kx 5v range 8-bit mcu with 8 t o 32k flash, 10-bit adc , 4 timers , spi, sci interf a c e not for new design memories ? 8 to 32 k du al vo lta g e high densit y flash (hd- flash) w i th read -out protection c a pability . in- application programmin g a nd i n - circuit pro - gr ammin g f o r hdf l ash de vices ? 3 8 4 t o 1k by te s r a m ? h dfla sh en dur an ce : 1 0 0 cycles, dat a ret e n - tio n : 20 year s a t 55 c clock , res e t and supply ma nage ment ? e nha nced low vo lta g e sup e rvisor ( l vd) fo r main su pply with pro g r a mma ble r e set t h re sh - olds and auxiliary voltag e detec t or (avd ) w ith interrupt capability ? c lock sources: cryst al/ c eramic res o nat o r os- c illators, internal r c osc illator, clock security syst em a n d bypass f o r exte rn al clo c k ? p ll f o r 2 x f r e que ncy mu ltip lica t i o n ? f ou r power saving mo des: halt , active- h alt , wa it a nd slow int e rrupt ma nag e ment ? n ested interrupt controller ? 10 interrupt vectors plus tr ap and r eset ? 9 /6 e xte r n a l in te rr up t line s ( o n 4 v e c to r s) u p to 3 2 i/ o port s ? 32/ 2 4 mult if unct i ona l b i dir e ctio na l i / o lines ? 22/ 1 7 alt e r nat e f unct i on lin es ? 12/ 1 0 high sink ou tp ut s 4 timers ? m ain clock c o ntroller with: r e al time bas e , beep and clock-out capabilities ? c o nf i gu rab l e wat c h dog t i me r ? 16- bit t i mer a wit h: 1 inpu t ca pt ur e, 1 out pu t co mpa r e , exte rn al clock in put , pwm a n d pulse g ene ra to r mod e s ? 16- bit time r b wit h: 2 inpu t capt u r es, 2 out pu t co mpa re s , pwm a nd pu lse g ene ra to r mo des 2 communica tion inte rfa c e s ? spi synchr on ous se ria l in te rf ace ? s ci as yn chr o no us se r i al in te r fac e 1 ana l og pe rip h era l ( l ow curre nt c oupling) ? 1 0- bit adc with up t o 12 r o b u st inp u t p o r t s ins t ruct ion se t ? 8 -bit data manipulation ? 6 3 basic instructions ? 1 7 main ad dr essin g mod e s ? 8 x 8 unsigned multiply instruction dev e lopmen t tools ? f ull har dwar e/ sof t war e de ve lop m ent pa ckag e ? i n-circuit testing capability de vi ce summar y tqfp44 10 x 10 sdip42 600 mil sdip 3 2 400 mil tq f p 3 2 7 x 7 features st72324j6 st72324k6 1 st72 324j4 st72 324k4 1 st7 2324j2 st72324 jk2 1 p r ogram memory - by tes f l as h 32 k f la sh 1 6 k f la sh 8 k ra m (s ta ck ) - b y t e s 1 0 2 4 ( 25 6) 51 2 ( 25 6) 3 8 4 ( 25 6) vo lta ge ran g e 3.8 v to 5. 5 v t e mp . ra ng e u p to -4 0c t o +1 25 c pa ck ag es s d i p 4 2, tq f p 44 10 x1 0, sd ip 3 2, tq f p 3 2 7x 7 1 fo r n ew desi g ns i n s t and ar d a nd i n dust ri a l a ppl i c at io ns, u se st7 2324b( j/ k) or der codes, re f er t o s epar at e d at a sheet 1 http://
table of contents 164 2/164 1 i n tro duc ti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pi n d escr i ptio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 r e gi ster & m e m o r y m a p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 flash pro g ram m e m o ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 i ntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 4. 2 m ain featur es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 4. 3 s tru c ture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 .3 .1 r e a d - o u t pr o tec tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. 4 i cc i n terface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4. 5 i cp ( i n- cir cui t pro g r a m m i n g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 i ap (in-application progr a mming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. 7 r e l ated do cum en ta ti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 .7 .1 r e g is ter d e s crip tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 c e ntral processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 i ntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 5. 2 m ain featur es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 5. 3 c p u r e gi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 su pply, reset a nd cloc k man a geme nt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 p h ase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6. 2 m ul ti- o sc il lato r ( m o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6. 3 r e set seq uen c e m a n a ger ( r sm ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 .3 .1 in tro d u c tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 . 3 . 2 a syn ch ro n o u s exte r n a l re set p i n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3.3 external power-on r eset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 . 3 . 4 i n t e r n a l lo w volt ag e de te cto r (l vd) re set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 . 3 . 5 i n t e r n a l wa tch d o g res e t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6. 4 sys te m integ r ity ma nag e m e nt ( s i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 . 4 . 1 l o w volt ag e de te cto r (l vd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4.2 a ux iliary v o ltage detector (avd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 .4 .3 l o w pow e r m o d e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 .4 .4 r e g is ter d e s crip tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 i n terru pts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 i ntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 7.2 m asking and proces sing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7. 3 i nterru pts and l o w po wer mo de s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7. 4 c o n c urr ent & nested ma nag e m e nt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7. 5 i nterru pt reg i ster desc rip t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.6 exter nal in te rrup ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 . 6 . 1 i/o po r t in te r r u p t se ns itivit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.7 exter nal in te rrup t control regi ster (eicr) . . . . . . . . . . . . . . . . . . . . . . . 38 8 po wer sa ving m o des . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 i ntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 8. 2 s l o w m o de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8. 3 w a i t m o d e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2 table of contents 164 3/164 8. 4 a c t i ve-h a l t and hal t m o d es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8 . 4 . 1 a ctive- hal t m o de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8 . 4 . 2 h al t m o d e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 i / o po rts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1 i ntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 . 2 . 1 i n p u t mo d e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 9 . 2 . 2 o u t p u t m o de s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 . 2 . 3 a lte r n a t e fun ctio n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9. 3 i /o po rt im pl em entatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9. 4 l ow po wer m o d es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9. 5 i nterru pts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9 . 5 . 1 i/o po r t im p l e m e n t a t ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1 0 o n -c hip peri p hera ls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10 .1 wa tc hdo g tim e r (wd g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1 0 . 1 . 1 in tro d u c t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1 0 . 1 . 2 ma in fea t u r es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 1 0 . 1 . 3 fu n ctio n a l de scr ipt i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1 0 . 1 . 4 ho w t o p r o g r a m th e wat ch d o g tim e o u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1 0 . 1 . 5 lo w pow e r m o d e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 1 0 . 1 . 6 ha rd wa re wa tc hd o g op tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 1 0 . 1 . 7 usin g ha lt m o de w i th th e wdg ( w dg ha lt o p t io n) . . . . . . . . . . . . . . . . . . . . . . . 54 1 0 . 1 . 8 in te rr up ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 1 0 . 1 . 9 re gis t er d e s crip t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.2 main clock c o n t r o ller w i th r eal time clock a nd beeper (mcc /rtc) . 56 1 0 . 2 . 1 pro g r a m m a b l e c p u cloc k p r e sca ler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2.2 clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 1 0 . 2 . 3 re al tim e clo ck tim e r (r tc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 1 0 . 2 . 4 bee p e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 1 0 . 2 . 5 lo w pow e r m o d e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 1 0 . 2 . 6 in te rr up ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 1 0 . 2 . 7 re gis t er d e s crip t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10 .3 1 6 - b it ti me r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 1 0 . 3 . 1 in tro d u c t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 1 0 . 3 . 2 ma in fea t u r es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 1 0 . 3 . 3 fu n ctio n a l de scr ipt i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 1 0 . 3 . 4 lo w pow e r m o d e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1 0 . 3 . 5 in te rr up ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 1 0 . 3 . 6 sum m a r y of tim e r m o d e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1 0 . 3 . 7 re gis t er d e s crip t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10 .4 ser ial per iphe ral in te rface ( spi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1 0 . 4 . 1 in tro d u c t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1 0 . 4 . 2 ma in fea t u r es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 1 0 . 4 . 3 ge n e r a l de scr ipt i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1 0 . 4 . 4 clo ck pha se a n d c l oc k po la rity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 1 0 . 4 . 5 err o r fla g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 1 0 . 4 . 6 lo w pow e r m o d e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1 table of contents 164 4/164 1 0 . 4 . 7 in te rr up ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 1 0 . 4 . 8 re gis ter d e s crip tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10 .5 ser ial co m m uni catio n s i n terfac e (s ci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 1 0 . 5 . 1 in tro d u c tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 1 0 . 5 . 2 ma in fea tu r es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 0 1 0 . 5 . 3 ge n e r a l de scr ipt i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 1 0 . 5 . 4 fu n ctio n a l de scr ipt i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 1 0 . 5 . 5 lo w pow e r m o d e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 1 0 . 5 . 6 in te rr up ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 1 0 . 5 . 7 re gis t er d e s crip t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 0 10 .6 1 0 - b it a/d co nverter (a dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 6 1 0 . 6 . 1 in tro d u c tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 1 0 . 6 . 2 ma in fea tu r es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 6 1 0 . 6 . 3 fu n ctio n a l de scr ipt i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 7 1 0 . 6 . 4 lo w pow e r m o d e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 7 1 0 . 6 . 5 in te rr up ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 1 0 . 6 . 6 re gis t er d e s crip t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 8 11 in struction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 0 11 .1 cp u ad dres s ing m o des . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 0 1 1 . 1 . 1 in he re n t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1 1 1 . 1 . 2 im m e d i at e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 11 1 1 . 1 . 3 dire ct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1 1 1 . 1 . 4 in de xe d (n o off se t, sho r t, lo ng ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 . 1 . 5 in dir e c t ( s h o r t, lo n g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 . 1 . 6 in dir e c t i n d e xed ( s h o r t, lo n g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2 1 1 . 1 . 7 re lat i ve m o d e (d ire ct, in d i re ct) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2 11 .2 i n struc ti on g r o u ps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 3 1 2 electri cal c har acteri s tics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 6 12 .1 par am eter c o n d itio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 6 1 2 . 1 . 1 min i m u m an d m a x i mu m va lu es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 6 1 2 . 1 . 2 ty pic a l va lue s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 6 1 2 . 1 . 3 ty pic a l cu rve s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 6 1 2 . 1 . 4 lo a d in g ca pa cit o r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 6 1 2 . 1 . 5 pin inp u t v o lt ag e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 6 12 .2 abs ol ute m axi m u m rati ngs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 7 1 2 . 2 . 1 volt ag e ch a r a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 7 1 2 . 2 . 2 cu rr en t c h a r act e r i st ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 7 1 2 . 2 . 3 th e r m a l ch a r a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 8 12 .3 o pera t i n g co ndi ti on s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 8 1 2 . 3 . 1 op e r a t in g co nd itio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 8 12 .4 l v d/ avd c h ara c teris t i c s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 9 1 2 . 4 . 1 op e r a t in g co nd itio ns wit h lo w v o lt ag e de te cto r (l vd) . . . . . . . . . . . . . . . . . . . . 1 1 9 12.4.2 aux iliary v o ltage dete ctor (avd ) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12 .5 su ppl y cu rren t char a cteri s tics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 0 1 2 . 5 . 1 cur rent c o n s um ptio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 0 1 2 . 5 . 2 sup p l y a n d cloc k m a na g e r s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2 1 2 . 5 . 3 on -c hip pe r i ph er a l s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 3 1 table of contents 164 5/164 12 .6 cl o c k a nd ti mi ng ch aracter i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4 1 2 . 6 . 1 ge n e r a l tim i n g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4 1 2 . 6 . 2 exte r n a l clo ck so ur ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4 12.6.3 cry stal and ceramic re sonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.6.4 rc os cillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 1 2 . 6 . 5 pll c h a r a ct e r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 8 12 .7 m e m o ry c h arac teristi c s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 9 1 2 . 7 . 1 ram a n d h a r d w a r e re gis t e r s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 9 1 2 . 7 . 2 fl ash m e m o ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 9 12 .8 em c char a cteri s tics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 0 12.8.1 functional ems (e lectro magnetic sus cepti bility ) . . . . . . . . . . . . . . . . . . . . . . . . 130 1 2 . 8 . 2 elec tr o m a g n e tic in te rfe r en ce ( e m i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 1 1 2 . 8 . 3 abs o lu te m a xim u m rat i ng s (ele ct rica l se n sitiv ity) . . . . . . . . . . . . . . . . . . . . . . . . 1 3 2 12 .9 i /o po rt pin ch aracter i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 3 1 2 . 9 . 1 ge n e r a l ch ar ac te rist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 3 1 2 . 9 . 2 ou tp u t dr ivin g cu rr en t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 12 .1 0 c o n tr ol pi n ch arac te ristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 6 1 2 . 1 0 . 1 a sy nc hr on o u s rese t pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 6 12.10.2icc sel/vpp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12 .1 1 t im er peri p her a l char a cteri s tics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 9 1 2 . 1 1 . 1 1 6 - b it tim e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 12 .1 2 c o m m uni catio n i n terface cha racter istics . . . . . . . . . . . . . . . . . . . . . . . . 1 4 0 1 2 . 1 2 . 1 spi - ser i al pe rip h e r a l i n t e r f a ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 0 12 .1 3 1 0- bit adc char a cteri s ti cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 2 1 2 . 1 3 . 1 a n a lo g po we r su p p ly a n d r e f e r e n ce pin s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 4 1 2 . 1 3 . 2 g en er a l pcb de sig n gu ide lin es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 4 1 2 . 1 3 . 3 a dc acc u r a c y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 5 1 3 pac kag e c har acteri s tics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 6 13 .1 pac kag e m e ch anic al data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 6 13 .2 ther m a l char a cteri s tics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 8 13 .3 so l d eri n g info rm atio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 9 1 4 st7 2 3 2 4 d evic e co nfig ur atio n a nd o r d e rin g info rm atio n . . . . . . . . . . . . . . . 1 5 0 14 .1 fl ash optio n bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 0 14 .2 fl ash devic e o rder i ng i n for m a t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 2 14 .3 si li co n id entific a tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 4 14 .4 de vel opm e nt to o l s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 5 1 4 . 4 . 1 soc ke t a n d emu l a t o r ada p t e r i n f o r m a t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 6 14.5 st7 applic ation n o tes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 1 5 kn own lim i tati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 15 .1 al l devi ces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 1 5 . 1 . 1 exte r n a l rc o p t i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 9 1 5 . 1 . 2 css fu n ctio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 9 1 5 . 1 . 3 saf e co nn e ctio n of o s c1 /o sc2 pin s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 9 1 5 . 1 . 4 un ex pe cte d re se t fe tc h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 9 1 5 . 1 . 5 cle ar ing a ct i ve int e r r u p t s ou tsid e in te rr up t ro ut ine . . . . . . . . . . . . . . . . . . . . . . . . 1 5 9 1 5 . 1 . 6 exte r n a l in te r r u p t m i sse d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 9 1 table of contents 164 6/164 1 5 . 1 . 7 16 -b it tim e r pwm m o de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 1 1 5 . 1 . 8 sci wr on g bre a k d u r a t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 1 15 .2 fl ash devic es o n l y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 1 1 5 . 2 . 1 in te rn al rc op er a t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 1 1 6 im po rtan t no tes o n st7 2 f3 24 b fla s h d evic es: . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 2 16.1 re set pin logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16 .2 wa ke-u p fro m activ e hal t m o de u s ing e x te rnal i n terru pts . . . . . . . 1 6 2 16 .3 pl l ji tter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 2 16 .4 ac ti ve h a lt pow e r c o n s um ptio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 2 16 .5 tim e r a r e gi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 2 1 7 rev i sio n histo r y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 1 to ob ta in th e m o st r e c e n t v e r sio n of th is da ta sh ee t, plea se ch eck at www.st . c o m >p ro duc t s>t echn ica l lit er at ur e>da ta sh ee t. plea se also pay sp ecial at t ent ion t o t h e se ct ion ? k no wn li mi tati ons? on p age 1 5 9 . st72324jx st72324kx 7/164 1 introduction the st7 232 4 de vices ar e memb er s of th e st7 mi- cr ocon tr olle r f a mily de sig ned fo r t he 5 v o per at ing ra nge . ? the 32- pin d e vice s ar e de sig ned fo r mid- ra nge applic ations ? the 4 2 / 44- pin d e vice s t a r get t h e sa me ra nge o f app lica t io ns req u ir ing mo re t h a n 24 i / o por ts. for a d escr i pt ion of t he d i ff e r en ce s bet ween st 723 24 an d st7 2 3 24b devices r e f e r t o section 14. 2 on p a g e 152 al l de vices a r e ba se d o n a comm on indu st r y - st an dar d 8 - bit cor e , fe at ur ing a n en han ce d inst ru c- tio n se t and a r e ava ilable wit h f l ash pr og ram memo ry. un der sof t war e con t r o l, all d e vice s can be placed in w a it, slow, active-halt or h a lt mode, red u cing po we r co nsump t io n whe n t h e ap plicat ion is in idle o r sta nd- by st at e. the enh an ce d in st ru ctio n set a nd add re ssing modes of the s t 7 offer bo th power and flexibility to so ft war e develo p e r s, e nab ling t he d e sign of hig h ly ef ficien t and comp act a p p lica t io n cod e . i n a ddit i on to st an dar d 8- bit da ta mana ge men t , all st7 m i cr o- co nt ro llers f eat ur e t r u e bit ma nipu lat i on , 8x8 u n - sig ned m u lt iplicat ion a nd ind i re ct add re ssing mode s. fi gure 1 . devi ce bl ock di agr a m 8- bit co re al u address and data bus os c 1 v pp con trol pro gram (8k - 32k bytes) v dd res e t port f pf7:6,4,2:0 time r a be ep po rt a ram (3 84 - 10 24 b y t e s ) port c 10 -bit adc v aref v ssa p ort b pb 4:0 port e pe 1:0 (2 bits) sc i timer b pa 7:3 (5 bits on j devices) port d pd5:0 spi pc 7:0 ( 8 b its ) v ss watch dog osc lv d os c 2 m e mory mc c/rtc/be ep (4 bi ts on k de vi ce s) (5 bi ts on j de vi ce s) (3 bi ts on k de v i ce s) (6 bits on j devices) (2 bits on k devices) ( 6 bit s o n j d e v ic es ) ( 5 bit s o n k de vic e s ) 3 st72324jx st72324kx 8/164 2 pin description figure 2. 42-pin sdip and 44-pin tqfp package pinouts mco / ain8 / pf0 beep / (hs) pf1 (hs) pf2 ocmp1_a / ain10 / pf4 icap1_a / (hs) pf6 extclk_a / (hs) pf7 v dd_0 v ss_0 ain5 / pd5 v aref v ssa 44 43 4 2 41 40 3 9 38 37 3 6 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 ei 2 ei3 ei 0 ei1 pb 3 (hs ) pb 4 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 ain4 / pd4 rdi / p e 1 pb 0 pb 1 pb 2 p c 6 / sck / icccl k pc5 / mosi / ai n1 4 pc4 / miso / iccdata pc 3 (h s ) / ic ap 1 _ b pc 2 (h s ) / ic ap 2 _ b p c 1 / ocmp 1 _ b / ain1 3 p c 0 / ocmp 2 _ b / ain1 2 v ss _1 v dd_1 pa 3 (h s) pc 7 / s s / ain1 5 v ss _2 reset v pp / iccsel pa7 (hs) pa6 (hs) pa5 (hs) pa4 (hs) pe0 / tdo v dd _2 osc1 osc2 38 37 36 35 34 33 32 31 30 29 28 27 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 39 40 41 42 ( h s) pb4 ain0 / pd0 ain12 / ocmp2_ b / pc0 ex tcl k _ a / ( h s) pf7 icap 1_ a / ( h s) pf6 ain1 0 / o c mp1 _ a / pf4 ( h s) pf2 bee p / ( h s) pf1 mco / ain8 / pf0 ain5 / pd5 ain4 / pd4 ain3 / pd3 ain2 / pd2 ain1 / pd1 v ss a v aref pb3 pb 2 pa 4 (h s ) pa 5 (h s ) pa 6 (h s ) pa 7 (h s ) v pp / iccs el r ese t v ss _2 v dd _2 pe 0 / t d o p e 1 / rdi pb 0 pb 1 os c 1 osc2 ei 3 ei0 ei 2 ei 1 21 20 17 18 19 ai n1 4 / mosi / pc5 iccda ta / miso / p c 4 ic ap1 _b / (h s) p c 3 ica p 2_ b/ (h s) p c 2 ai n1 3 / o c m p1 _b / pc 1 26 25 24 23 22 pc6 / sck / icccl k pc7 / ss / ain15 pa3 ( h s ) v dd_ 1 v ss _1 ei x associated external interrupt vector (hs) 20 ma hi g h si n k ca pa bi l i t y st72324jx st72324kx 9/164 p i n d escr i ption (con t?d ) figure 3 . 32 -pin sdip pa cka ge pin out figure 4. 32-pin tqfp 7x7 package pinout 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 ( h s) pb4 ain0 / pd0 ain1 4 / mo si / pc5 icc d ata / miso / pc4 icap 1_ b / ( h s ) pc3 icap 2_ b / ( h s ) pc2 ain13 / ocmp1_ b / pc1 ain12 / ocmp2_ b / pc0 ex tcl k _ a / ( h s) pf7 bee p / ( h s) pf1 mco / ain8 / pf0 v ss a v are f ain1 / pd1 ic ap1 _a / (h s) p f 6 ocmp1_ a / ain10 / pf4 pb 3 pb 0 pc6 / sck / icccl k pc7 / ss / ain15 pa3 (hs ) pa4 (hs ) pa6 (hs ) pa7 (hs ) v pp / iccsel osc2 osc1 v dd _2 pe0 / td o pe1 / rdi v ss _2 re set ei0 ei 3 ei 2 ei 1 eix a s s o c i at ed ex te rn al int e r r u p t v e c to r (hs) 2 0 m a h ig h s in k c a p a b il ity iccda ta / miso / pc4 ain14 / mosi / pc5 iccclk / sck / pc6 ain15 / ss / pc7 (hs) pa3 ain13 / ocmp1_b / pc1 icap2_b / (hs) pc2 icap1_b / (hs) pc3 32 31 30 2 9 28 27 2 6 25 24 23 22 21 20 19 18 17 9 1 01 1 1 2 1 3 1 41 5 1 6 1 2 3 4 5 6 7 8 ei 1 ei 3 ei 0 ocmp 1 _ a / a i n1 0 / pf4 icap 1_ a / ( h s) pf6 ex tcl k _ a / ( h s) pf7 ain12 / ocmp2_ b / pc0 v are f v ss a mco / ain8 / pf0 b e e p / ( h s) pf1 v pp / iccs el pa 7 (h s ) pa 6 (h s ) pa 4 (h s ) os c1 os c2 v ss _2 re se t pb 0 pe1 / rdi pe0 / tdo v dd _2 pd1 / ain1 pd0 / ain0 pb4 (hs) pb3 ei2 ei x a ss oc ia ted e xt ern a l i n t e rru pt ve ct or (h s ) 20 ma hig h si nk ca pa bi lity 1 st72324jx st72324kx 10/164 p i n d escr i ption (con t?d ) for e x t e r n a l p i n conn ectio n gu idelin es, r e f e r t o see ? e lectri cal characteri stics ? o n pag e 1 1 6 . lege nd / abbre v iat i o n s fo r t able 1 : type: i = inp u t , o = out pu t, s = su pply in put level: a = ded i ca te d ana log in put in/output level: c = cmos 0.3v dd /0 .7 v dd c t = cmos 0. 3v dd /0 .7 v dd with input trigger output lev e l: hs = 20ma h i gh sink (on n- buf f e r o n ly) po rt and co nt rol con f ig ur at ion: ? i n p u t : f l oa t = f l oa tin g , wp u = weak pu ll-up , in t = in te rr upt 1) , an a = analo g por t s ? o u tp ut : od = op e n dr ain 2) , pp = push - pu ll re fe r t o ?i/o p o rts? o n pa g e 45 f o r m o r e de ta ils on t h e so ft wa re co n f ig ur at ion o f th e i/o p o r t s. the r eset configurati on of ea ch pin is shown in bold. th is configuration is valid as long as the device is in res e t state . tabl e 1. devi ce pi n de sc rip t i on pin n pin name type level port ma i n function (af t er re set) alternate function tq f p 44 sdip42 tq f p 32 sdip32 input outp ut input output fl oat wpu int ana od pp 6 1 30 1 pb4 (hs ) i/o c t hs x ei 3 x x p o r t b 4 7 2 31 2 p d0/ai n 0 i /o c t x x x x x port d0 ad c analog inp u t 0 8 3 32 3 p d1/ai n 1 i /o c t x x x x x port d1 ad c analog inp u t 1 9 4 pd2/ain 2 i/o c t x x x x x port d2 ad c analog inp u t 2 10 5 p d3/ai n 3 i /o c t x x x x x port d3 ad c analog inp u t 3 11 6 p d4/ai n 4 i /o c t x x x x x port d4 ad c analog inp u t 4 12 7 p d5/ai n 5 i /o c t x x x x x port d5 ad c analog inp u t 5 13 8 1 4 v are f s a nalog reference voltage for adc 14 9 2 5 v ss a s a nalog ground voltage 15 10 3 6 pf0/mco/ain 8 i/o c t x ei 1 x x x p o r t f 0 ma i n clo c k out (f cpu ) adc a nalog input 8 16 11 4 7 pf1 (hs)/be e p i /o c t hs x e i 1 x x p ort f1 beep signal output 17 12 pf2 (hs) i/o c t hs x ei1 x x p ort f2 18 13 5 8 pf4/ocmp1_a / ain10 i/ o c t x xx x x p o r t f 4 timer a o u t- put com - pare 1 adc a nalog input 10 19 14 6 9 pf6 (hs)/icap1_a i/o c t hs x x x x p ort f6 timer a input capture 1 20 15 7 1 0 pf7 (hs)/ extclk _ a i/ o c t hs x xx x p o r t f 7 timer a ex ternal cloc k source 21 v dd_0 s d igital main supply voltage 22 v ss _0 s d igital ground voltage 23 16 8 1 1 pc0/ocmp 2_b/ ain12 i/ o c t x xx x x p o r t c 0 timer b o u t- put com - pare 2 adc a nalog input 12 1 st72324jx st72324kx 11/164 no tes : 1. in the interrupt input column, ?eix? defines the associated external interrupt vector. if the weak pull-up 24 17 9 12 pc1/ocmp 1_b/ ain13 i/ o c t x xx x x p o r t c 1 timer b o u t- put com - pare 1 adc a nalog input 13 25 18 10 13 pc2 (hs ) /icap2_b i/o c t hs x x x x p ort c2 timer b input capture 2 26 19 11 14 pc3 (hs ) /icap1_b i/o c t hs x x x x p ort c3 timer b input capture 1 27 20 12 15 pc4/miso/iccda - ta i/ o c t x xx x p o r t c 4 sp i master in / slav e o u t data icc data in- pu t 28 21 13 16 pc5/mosi/a in14 i/o c t x xx x x p o r t c 5 sp i master o u t / slav e in data adc a nalog input 14 29 22 14 17 pc6/sck/iccc lk i/o c t x xx x p o r t c 6 sp i serial clock icc clock output 30 23 15 18 pc7/ss /a in15 i/ o c t x xx x x port c7 sp i slave select ( a c- ti ve low) adc a nalog input 15 31 24 16 19 pa3 (hs ) i/o c t hs x ei0 x x port a3 32 25 v dd_1 s d igital main supply voltage 33 26 v ss _1 s d igital ground voltage 34 27 17 20 pa4 (hs ) i/o c t hs x xx x p o r t a 4 35 28 pa5 (hs ) i/o c t hs x xx x p o r t a 5 36 29 18 21 pa6 (hs ) i/o c t hs x tp o r t a 6 1) 37 30 19 22 pa7 (hs ) i/o c t hs x tp o r t a 7 1) 38 31 20 23 v pp /iccsel i must be tied low. in the flash pro- gram ming mode, this pin acts as the programming voltage inp u t v pp . see section 12.10.2 f o r mor e det ai ls . 39 32 21 24 rese t i/ o c t top priority non maskable interrupt. 40 33 22 25 v ss _2 s d igital ground voltage 41 34 23 26 osc 2 o r esonator osci llator inv e rter output 42 35 24 27 osc 1 i external c l ock input or resonator os- cillator in verter inp u t 43 36 25 28 v dd_2 s d igital main supply voltage 44 37 26 29 pe0/tdo i/o c t x x x x p or t e0 sc i trans mit d a ta o u t 1 3 82 73 0 p e 1 / r d i i / o c t x x x x p or t e1 sc i rec e i v e dat a i n 2 3 92 83 1 p b 0 i / o c t x ei 2 x x p o r t b 0 caution: negative current injection not allowed on this pin 5) 3 4 0 pb1 i/o c t x ei 2 x x p o r t b 1 4 4 1 pb2 i/o c t x ei 2 x x p o r t b 2 5 4 22 93 2 p b 3 i / o c t x ei2 x x p ort b3 pin n pin name type level port ma i n function (af t er re set) alternate function tqfp44 sdip42 tqfp32 sdip32 input output input output fl oat wpu int ana od pp 1 st72324jx st72324kx 12/164 c o lumn (wpu) is merged with t h e int e r r up t colu mn (in t ), t h e n t he i / o co nf igur at ion is pu ll-u p int e r r up t in put , else th e conf igu r a t io n is f l oat in g int e rr up t inp u t . 2. in t h e ope n dr ain o u t p u t colum n , ?t? def ine s a tr ue o pen dra i n i / o (p- b u f f e r an d pr ot ectio n dio de t o v dd ar e not imple m en te d) . see see ? i /o po rt s? on pa ge 4 5 . a nd section 12.9 i/o port pin ch arac te r- isti cs fo r m o re d e t a ils. 3. osc1 a n d osc2 p i ns conn ect a cryst al/ c e r a m ic re so nat or , or an ext e rn al sou r ce to t he on- ch ip o s cil- lator; s e e sec t ion 1 in troduction an d sec t ion 12.6 cloc k a nd timing char a cteristics fo r mor e det a ils. 4. on t h e ch ip, each i / o po rt has 8 p ads. pa ds th at ar e no t b ond ed t o e x t e r n a l p i ns ar e in in put pu ll-u p co n- fig u r a t i on af te r re se t. th e co nf igur at ion of t h e s e p ads m u st be ke pt at r e set st at e to avoid ad de d cur r e n t co nsump t io n. 5 . fo r d e ta ils re fe r to sect ion 1 2 . 9 . 1 on pa ge 1 3 3 1 st72324jx st72324kx 13/164 3 register & memory map as sh own in f i gur e 5 , t he mcu is cap able of ad- dr essin g 64k byte s of memo rie s an d i/ o re gist ers. the availa ble mem o ry locat i ons con s ist o f 128 byte s o f r e g i st er locat i on s, up to 102 4 byt e s of ram an d up t o 32 kbyt es of u s e r pr ogr am me mo- ry. the ram sp ace in clu des up t o 25 6 b y t e s f o r th e st ack fr om 01 00h t o 0 1 ffh . the high est a d d r ess byt e s co nt ain th e user r e set and in te rr upt vecto r s. imp o rt an t: m e mo ry lo ca t i ons mar k e d as ?re- se rv ed ? mus t n e v e r be a c ce ss ed . ac ce ss i n g a r e - served area can have unpredictable effects on the device. figure 5 . memo ry map 00 00 h ram program memory (32k, 16k or 8k) interrupt & reset vectors hw registers 0080h 00 7f h 7ff f h (see table 2 ) 8 000 h ff dfh ff e0h ff ff h (see table 8 ) 04 80 h reserved 04 7f h s hort addres sing ram (zero page) 256 by tes s tack 16-bit addressing ram 01 00 h 01 ff h 02 7fh 00 80 h 0200h 00 ff h 32 kbytes 8000h ff ffh (1024, or 047fh 16 kbytes c0 00 h 512 or 384 bytes) 8 kbytes e0 00 h 1 st72324jx st72324kx 14/164 tabl e 2. hardw a re reg i s t er m a p addres s b lock register label r e gister name reset status remarks 0000h 0001h 0002h port a 2) padr paddr paor port a data regis t er port a data direction regis t er port a option register 00h 1) 00h 00h r/w r/w r/w 0003h 0004h 0005h port b 2) pbdr pbddr pbor port b data regis t er port b data direction regis t er port b option register 00h 1) 00h 00h r/w r/w r/w 0006h 0007h 0008h port c pcdr pcddr pcor port c data regis t er port c data direction regis t er port c option register 00h 1) 00h 00h r/w r/w r/w 0009h 000ah 000bh port d 2) pdadr pdddr pdor port d data regis t er port d data direction regis t er port d option register 00h 1) 00h 00h r/w r/w r/w 000ch 000dh 000eh port e 2) pedr peddr peor port e data regis t er port e data direction regis t er port e option register 00h 1) 00h 00h r/w r/w 2) r/w 2) 000fh 0010h 0011h port f 2) pfdr pfddr pfor port f data register port f data direction register port f option register 00h 1) 00h 00h r/w r/w r/w 0012h to 0020h r e s e rved area (15 bytes) 0021h 0022h 0023h spi spidr spicr spicsr spi data i/o register spi control register spi control/status r e g i ster xxh 0xh 00h r/w r/w r/w 0024h 0025h 0026h 0027h itc isp r 0 isp r 1 isp r 2 isp r 3 int e rr upt soft ware pr iority r egister 0 int e rr upt soft ware pr iority r egister 1 int e rr upt soft ware pr iority r egister 2 int e rr upt soft ware pr iority r egister 3 ffh ffh ffh ffh r/w r/w r/w r/w 0028h eic r external interrup t c ontro l register 00h r/w 0029h flas h f csr f lash contro l/s t atus register 00h r/w 002ah w atchdog w dg cr watchdog control register 7fh r /w 002bh s i s ic sr system integrity c ontrol status register xxh r/w 002ch 002dh mc c mccs r mccb cr main clo ck control / s t atus register main clo ck controller: beep control regis t er 00h 00h r/w r/w 002eh to 0030h reserved area (3 bytes) 1 st72324jx st72324kx 15/164 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh time r a tacr2 tacr1 tacsr taic 1 h r taic 1 l r taoc1hr taoc1lr tachr taclr taachr taaclr taic 2 h r taic 2 l r taoc2hr taoc2lr tim e r a control register 2 tim e r a control register 1 tim e r a control/status r e gister 3) 4 ) tim e r a input capture 1 h i gh r e gister tim e r a input capture 1 low register tim e r a output compare 1 high r egister tim e r a output compare 1 low regis t er tim e r a counter high register tim e r a counter low regis t er tim e r a alternate c ounter high register tim e r a alternate c ounter low register tim e r a input capture 2 h i gh r e gister 3) tim e r a input capture 2 low register 3) tim e r a output compare 2 high r egister 4) tim e r a output compare 2 low regis t er 4) 00h 00h xxxx x0xx b xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h reserved area (1 byte) 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh time r b tbcr2 tbcr1 tbcsr tbic 1 h r tbic 1 l r tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic 2 h r tbic 2 l r tboc2hr tboc2lr tim e r b control register 2 tim e r b control register 1 tim e r b control/status r e gister tim e r b input capture 1 h i gh r e gister tim e r b input capture 1 low register tim e r b output compare 1 high r egister tim e r b output compare 1 low regis t er tim e r b counter high register tim e r b counter low regis t er tim e r b alternate c ounter high register tim e r b alternate c ounter low register tim e r b input capture 2 h i gh r e gister tim e r b input capture 2 low register tim e r b output compare 2 high r egister tim e r b output compare 2 low regis t er 00h 00h xxxx x0xx b xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate registe r sci control register 1 sci control register 2 sci extended receive p r escaler register reserved area sci extended transm i t prescaler register c0h xxh 00h x000 0000h 00h 00h -- - 00h read only r/w r/w r/w r/w r/w r/w 0058h to 006fh r e s e rved area (24 bytes) 0070h 0071h 0072h ad c adccsr adcdrh adcdrl control/status regis t er data hig h register data low register 00h 00h 00h r/w read only read only 0073h 007fh r e s e rved area (13 bytes) addres s b lock register label r e gister name reset status remarks 1 st72324jx st72324kx 16/164 lege nd : x = u n d e f in ed , r / w= re ad /w rite no tes : 1. the con t e n t s o f t h e i/ o p o rt dr r egi st er s a r e r e a dab le on ly in out pu t con f ig ur at ion. i n inp u t co nf igur a- t i on, th e va lues of th e i/ o pin s a r e r et ur ned in st ea d of th e dr re giste r cont en ts. 2. t he bit s a s so cia t e d wit h un availa ble pin s mu st always kee p th eir r e set va lue. 3. t he time r a i n put ca pt ur e 2 pin is not availab l e (n ot b o n ded ). ? i n flash de vices: th e taic2hr a n d tai c 2lr re giste r s ar e not pr esent . bit 5 of t h e tacsr reg i st e r (i cf2) is fo rced by har dwar e t o 0. con s e q u ent ly, t he cor r e s p ond ing in te rr upt ca nno t b e used. 4. t he time r a o u t p u t comp ar e 2 pin is n o t availab l e (n ot b ond ed ). ? the taoc2hr and taoc2lr regis t ers are write only , reading them will return undefined values . bit 4 of t h e tacsr re giste r (o cf 2) is f o r c e d b y ha rdwa re t o 0 . co nseq uen tly, t h e cor r esp ond ing in- t e r r up t can not be used . ca ution: the t a i c 2hr a nd tai c 2 l r reg i ste r s and t h e i c f2 an d ocf2 f l ag s ar e no t pr esen t in fla s h d e - v i ces but are present in t he emulator. for compatibilit y with the emulator, it is recommended to perform a d u m m y ac ce ss (r ea d or w r ite ) to th e taic 2l r a n d ta oc 2l r r e gist er s to cle a r th e in te rr up t flag s. 1 st72324jx st72324kx 17/164 4 flash program memory 4. 1 in tro duct i o n t h e st 7 du a l vo lta g e h i gh d e n s ity f l as h (hdflash) is a no n- vo lat ile mem o r y t hat can be elect r ically er ased a s a sin g le b l ock o r b y ind i vidu- al secto r s an d pr ogr am med o n a byt e -b y-byte ba- sis using a n exte rn al v pp supply. the hdf l ash devices can b e pro g r a mme d and er ased o f f - b o a r d ( p lu gge d in a p r o g ra mmin g t ool) or on -b oar d using i c p ( i n - circuit prog ra mming ) or iap (i n- applicat io n pr og ra mming ). the ar ray ma tr ix or gan isa t ion a llows each se ct or to be e r a s e d a n d r epr ogr am med with out af fe ct ing ot her se ct or s. 4. 2 mai n fea t ur es t h re e f l as h pr og r a m m ing m o de s: ? i n s e r t i on in a pr ogr amm i ng to ol. i n th is mod e , all se ct or s inclu d ing op ti on byte s can be pr o- gr amme d or e ra s e d . ? i cp (i n- circuit pro g ra mmin g ). i n t h is mode , a l l se cto r s in clu d ing o p t i on byt e s can be pr o- gr amme d o r e r ased with out r e mo vin g t he de- vice f r o m th e app licat ion bo ar d. ? i ap (in-application pr og r a m m i ng ) in th is mod e , a ll sect ors exce pt se ct or 0 , can be pr o- gr amme d o r e r ased with out r e mo vin g t he de- vice f r om t he ap plicat ion b o a r d a nd while t h e app licat ion is r u n n ing . ict ( i n-cir cu it test ing) f o r do wn load ing and execut ing use r app licat ion t e st pa tt e r ns in ram re ad- ou t pr ot ect i on re gi st e r ac ce ss sec u r i ty system (ras s) to pre v e n t accid ent al pr og ra mming o r er asing 4. 3 struc t u r e t h e f l as h m e m o ry is or ga n i se d in se cto r s a n d ca n be used fo r bot h cod e and d a t a sto r ag e. de pen ding on t h e overa ll flash me mor y size in t h e micr ocon tr olle r de vice, th er e ar e up t o th re e user se ct or s ( see ta ble 3 ). each of t hese sect or s can be era sed inde pen de nt ly to avoi d u nne ce ssar y era s in g o f t h e whole flash memo ry when on ly a p a r t i al e r as ing is re qu ir ed . the f i rst two sect ors ha ve a fixed size of 4 kbyt es (see fig u r e 6 ) . th ey a r e ma pp ed in t he up pe r par t of t he st7 add re ssing spa c e so t h e r e set a nd in- te rr upt vect or s are locat e d in secto r 0 ( f000 h- ffffh ). tabl e 3. sect ors a vai l a bl e i n fla s h de vi ces 4. 3. 1 re ad- out pro t e cti o n re ad- ou t pr ot ect i on, wh en sele ct ed , p r ovid es a pro t e ctio n ag ainst pro g r a m me mor y co nt ent ex- tr actio n an d aga inst writ e access t o flash me mo- ry. eve n if no pr ot ect i on can be consid ere d as t o - ta lly u nbr ea ka ble, t he f e a t u r e pr ovides a ver y high level of pr ot ectio n f o r a ge ner al pu rp ose micro c o n - troller. i n f l ash devices, t h is p r o t e c t i on is r e mo ved by r e - p r og ra m m i ng th e op tio n . in th is cas e , th e en tir e pro g r a m mem o r y is f i r s t aut om at ica lly er ased . re ad- ou t p r o t e c t i on se lect ion d epe nds o n t he d e - v i ce ty pe : ? in flash de vices it is e n a b led a nd r e mo ve d thr o ug h th e f m p_ r bit in th e op tio n b yte . ? in ro m d e vices it is en ab led by mask o p t i on sp ecifie d in th e op tio n list. figure 6 . memo ry map a nd sect or addres s flas h siz e (bytes) available sector s 4k sector 0 8k sectors 0,1 > 8k sectors 0,1, 2 4 kbytes 4 k bytes 2k b ytes se c t or 1 se c t or 0 16 kbytes sector 2 8k 16k 32k 60k fla sh fff fh ef ff h df ff h 3ff f h 7ff f h 1000h 24 kby t es memory si ze 8kby t e s 40 kbytes 5 2 kb yt es 9ff f h bfffh d7ffh 4k 10k 24k 48k 1 st72324jx st72324kx 18/164 flash program memory (cont ?d ) 4. 4 icc i n t e rf ac e icc nee ds a m i nimum of 4 a nd u p t o 6 pins t o be co nne ct e d t o t he pr og ra mming t o o l ( s ee figu re 7 ). t h es e pin s ar e: ? reset : device re se t ?v ss : de vic e po we r su pp ly g r ou nd ? i cccl k : i c c ou tp ut ser i al clock pin ? i ccdat a: icc inpu t/ ou tp ut se rial da t a pin ? i ccse l /v pp : pr og ra mming volt ag e ? o sc1(o r o s ci n): main clock inpu t f o r exte r- nal sour ce (o pt iona l) ?v dd : ap plicat ion boa rd power supp ly (op t io n- al, see f i gur e 7 , n o t e 3 ) figure 7 . typ i c a l icc int e rf ace no tes : 1. i f th e i c ccl k or i c cdata pin s ar e o n ly used as ou tp ut s in t h e app licat ion, n o signa l isolat io n is necessar y . as soo n as t h e pr og ra mming t ool is plug ged t o t h e bo ar d, even if an icc sessio n is n o t in pr og re ss, th e i c cclk a nd i c cdata pin s are not availa ble f o r t he a pplicat io n. if th ey ar e used as inpu ts by t he a p p lica t io n, iso l at ion su ch as a seria l re sist or has t o im pleme n t e d in case a n o t h e r de- vice f o r c e s t h e sign al. re fe r to th e prog ra mming too l d o cume nt at ion f o r re co mmen ded resist or val- ues. 2. dur i ng t h e icc session , t he pr og ra mming t o o l must cont rol the res e t p i n. t h is can le ad t o con- flict s b e t w e e n t h e pr ogr am ming t o o l an d th e a ppli- c a t i on re se t c i rc uit if it d r iv es mo r e t h a n 5m a a t h i g h lev e l (p us h pu ll ou tp ut o r pu ll-u p r e s i sto r < 1 k) . a sc ho tt ky dio d e ca n be use d t o iso l at e th e ap p li- c a tion res e t circ uit in this case. when using a cla s sical rc ne twor k with r>1k or a r e set m an- age men t i c wit h op en dr ain ou tp ut a nd pu ll-u p r e - sist or>1 k, no ad dit i ona l comp on ent s ar e ne ede d. i n a ll ca se s th e us er m u st en su re tha t n o ex te rn al reset is g ene ra te d b y th e a pplicat ion du rin g t h e i cc session. 3. t he u s e o f pin 7 of t h e icc co nne ct or de pen ds on t he pro g r a mmin g too l a r chit ect u re . th is pin m u st b e co nn e cte d wh en usin g m o st st pr og ra m - m i n g t o ols ( i t is us ed to m o nit o r th e a p p lica t io n power sup p ly). ple a se r e f e r t o th e pr og ra mming tool ma nua l. 4. pin 9 has to be con nect ed t o t he o s c1 o r os- ci n p i n of th e st7 when t h e clo c k is no t a v a ilable in th e ap p lica t io n or if t h e s e le ct ed c l oc k op tio n is not pr og ra mmed in t h e op tio n byt e . st7 devices w i th multi-osc illator c a pability need to have osc 2 gro u n ded in t h is ca se. icc con nect or iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 p rogr amming to ol icc connector application board icc ca ble (s ee n o te 3) 10k ? v ss iccsel/vpp st 7 c l2 c l1 osc1 osc2 optional see note 1 see note 2 a ppl ic ation re set sour ce application i/o (see note 4) in some c ase s 1 st72324jx st72324kx 19/164 flash program memory (cont ?d ) 4.5 icp (in- circ uit pr ogra m ming) t o pe rf or m i c p th e m i cr oc on tr olle r m u st b e s witc h ed to ic c (in-circu it co mmun ica t ion) m ode by a n ext e rn al cont ro ller o r pr og ram m ing t o o l . d e p e n d i ng o n t h e icp co de do wn lo ad ed in ram , flash me mor y pr og ram m ing can b e f u lly cust om- ize d ( num ber of byt e s to pr ogr am, pr og ra m loca- t i ons, or selection serial communication interf ac e fo r do wn load ing ). wh en using an stmicro e lect ro nics or th ird - p a rt y pr ogr amm i ng t o o l th at supp or ts i c p a nd t h e spe- cif i c microcon t r olle r d e vice , t h e user n eed s o n ly to imple m en t t he i c p ha rd wa re in te rf ace on t h e ap- plicat ion b oar d ( s e e fig u r e 7 ) . f o r m o re det ails on th e p i n lo ca tio n s, re fe r t o th e d e vice p i nou t de- scr i pt ion. 4.6 iap (in- app l ica t ion progr ammin g ) this mo de u ses a boo t l o a der pr og ram pr eviously st or ed in se ct or 0 by th e user ( i n i c p mo de or by plug ging th e device in a pr ogr am ming t o o l ). this m ode is f u ll y co nt ro lled by user sof t war e . this allows it t o be a dap te d t o th e user app lica t ion, (u s- er -de f in ed st ra te gy fo r e n t e ri ng p r og ra mming mod e , cho i ce of co mmu n icat ions pro t ocol u sed to fe tch th e dat a to be st ore d , e t c. ). fo r examp l e, it is possible t o do wn load co de f r o m th e spi , sci , usb or can int e r f a c e an d pro g r a m it in th e flash. i a p mode ca n b e used to pr ogr am a n y of th e fla s h se ct or s e x ce pt se cto r 0, which is wr it e/ er ase pr o- tec t ed to allow recovery in case errors occur dur- ing t he pr og ra mming o per at ion . 4. 7 re la te d doc u ment at io n for det ails on flash p r og ra mmin g an d i c c pr ot o- co l, re fe r to t h e st7 flash pro g r a mmin g re fe r- ence manu al a nd to t he st 7 i c c pr ot ocol re fe r- ence ma nua l . 4. 7. 1 re gi ste r de sc rip t i o n flash control/status register (fc sr) re ad / w r i te r e s e t va lue : 00 0 0 00 00 ( 0 0h ) this re giste r is re se rved fo r u s e by pr og ra mming tool sof t wa re. it co nt ro ls t he flash pr og ra mming and e r a s in g ope ra tio n s. table 4. flash cont rol/stat u s re gi s t er addr ess a nd re se t val u e 70 0 000 000 0 addr ess (hex.) register label 76543 210 0029h fc sr r e s e t v a l u e 000 00 000 1 st72324jx st72324kx 20/164 5 central proce ssing unit 5. 1 introduct i o n t h is cpu ha s a fu ll 8- bit ar ch ite c tu re a n d co nt ain s six int e r nal r egist er s allo win g ef f i cie n t 8 - b i t da ta man i pula t io n. 5. 2 main feat ures en able execut ing 63 basic in st r u ctio ns fast 8- bit by 8 - b i t mu ltip ly 17 m a in add re ssing mo des ( w it h ind i rect add ressing m ode ) t w o 8- bit in de x r e gist er s 16- bit st ack p o int e r low power hal t a n d wait m ode s pr ior i ty maskab l e har dwar e int e r r u p t s n o n - ma sk ab le so ftw ar e/ ha r d wa r e in te r r u p t s 5. 3 cpu reg i sters the 6 cpu re giste r s sh own in fi gur e 8 ar e no t pre s e n t in t h e m e mo ry m app ing an d ar e a c ce ssed by spec ific instructions. accumulator (a) the accu mula to r is a n 8- bit g ene ra l p u rp ose re g- ist e r u s e d to ho ld ope ra nds and t he re sult s of t h e arit hm et ic and lo gic calculat ion s an d t o man i pula t e dat a. ind ex regi st ers ( x and y) t h e s e 8 - bit r e gist er s a r e us ed to cr ea te ef fe ctiv e add re sses or as te mpo r a r y sto r ag e ar ea s f o r da ta m a n i pu lat i on . ( t he cr o ss- asse m b le r ge n e r a t e s a pre c e d e in st r u ctio n (pre) t o indicat e t h a t t he f o l- lowing instruc t ion refers to th e y r e g i st er .) the y re giste r is not af f e cte d by th e int e r r u p t a u t o - mat i c p r oced ur es. pr ogra m count er ( p c) the pr og ram cou n t e r is a 1 6 -b it r egist er con t a i ning th e ad dr ess o f th e ne xt in st ru ct io n t o be execut ed by t he cpu. i t is mad e o f two 8- bit r egist er s pcl (pro gr am coun te r lo w which is t h e l s b) and pch (pro gr am coun te r high which is t h e m s b) . figure 8 . cpu regist ers a c cumula t or x inde x reg i ster y inde x reg i ster stack pointer conditio n co de r e gis t er p r ogr am c o unter 70 1c 1i1hi0nz res et v alue = rese t vect o r @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 rese t value = stack higher address reset va lue = 1x 11x 1x x reset v a lue = xxh rese t v a lue = xxh reset v a lue = xxh x = undefined v a lue 1 st72324jx st72324kx 21/164 c e ntral processing unit (c on t?d ) co ndition code regist er ( c c) re ad/ writ e r e s e t va lue : 11 1x 1x xx the 8-b i t co ndit i on co de r e g i st er cont ain s th e in- te rr upt ma sks an d f our f l ags re pr esen ta tive o f t h e re su lt o f t he in st r u ctio n just execut ed . th is r e g i st er ca n also b e ha nd led b y t h e push and pop in- s t ruct ions. the s e b i ts can be individu ally te st ed a n d / o r con- trolled by spec ific instructions. ar it hmet ic m a na gemen t bit s bi t 4 = h h a lf carry . this bit is set by ha rd wa re wh en a ca rr y o c cur s be- twee n b i t s 3 a nd 4 o f t he al u du ring a n add or a dc instructions. it is re se t b y ha rd wa re d u r i n g th e sa me inst ru ct ion s . 0: no ha lf car r y has occurr ed . 1: a ha lf car r y h a s occu rr ed. this bit is tested usin g the jrh or jr nh instruc - tio n . th e h bit is usef ul in bcd a r it hme t ic su br ou- tin e s . bi t 2 = n ne gat ive . this b i t is set a nd cl ear ed by h a r d war e . i t is r epr e- s e n t a t iv e o f t h e re su lt s i gn of th e la st ar ith m et ic, logical or da ta ma nipu lat i on . it ?s a co py o f th e r e - su l t 7 th b i t. 0 : t h e r e su lt of th e la st op e r a t io n is po sit i ve o r nu ll. 1: t he re sult o f t he last ope rat i o n is ne gat ive ( i .e . t h e mo st signif i cant bit is a log i c 1) . this bit is ac cessed by the jrmi and jrpl instruc - tio n s . bi t 1 = z ze ro . this bit is se t and clear ed by h a r d ware . this b i t in- dicat e s t h at t h e result of th e last arit hm et ic, log i ca l or da t a manip u la tio n is zer o . 0: th e re su lt o f t he last o p e r at ion i s dif f e re nt fr om zero. 1: th e re su lt o f t he last o p e r at ion i s zero . this bit is ac cessed by the j req and jr ne test inst ructions. bi t 0 = c ca rr y/ bo rr ow. this bit is set a nd cle a re d b y har dwar e a n d so ft - wa re. i t in dicat e s an over f l ow or a n u nde rf low h a s occu rr ed du rin g th e last a r it hme t ic op era t i on. 0: no over f l ow o r un der f l ow h a s o ccu rr ed. 1: an o v e r f l ow or un de rf low has occu rr ed. this bit is driven by the scf and rc f ins t ructions and t e st ed b y t he jrc an d jrnc inst ru ct ion s. i t is also af fe ct e d by t h e ?bit t e st an d br anch ? , shi f t and r o ta te ins t r u ct ion s. int e rr upt ma nag e ment bit s bit 5, 3 = i1 , i 0 in te rr up t the co mbin at ion of th e i 1 a n d i0 bit s gives t he cu r- rent interrupt s o ftware priority. these two b i ts ar e set / c le ar ed b y h a r d war e when ent er ing in int e r r u p t . the lo ad ed valu e is given by th e corr espo ndin g bit s in t he in te rr upt sof t wa re p r i- orit y r e g i st er s ( i xspr). t hey ca n be a l so set / c l ea r e d by so ft wa re w i th t h e rim , si m, i r et , halt , wfi a nd push/ p op instr u ct ions. se e th e in te rr upt mana ge men t ch apt er f o r mo re det ails. 70 11 i 1 h i 0 n z c interrupt software pr i o ri ty i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable ) 1 1 1 st72324jx st72324kx 22/164 c e ntral processing unit (c on t?d ) s t ack pointer (sp) re ad/ writ e re se t valu e: 0 1 ffh t h e st ac k poin te r is a 16 -b it r e g i st er w h ic h is a l - wa ys po int i ng t o t he n e xt f r e e locat i on in th e sta c k. it is th en de cr eme n t e d af t e r d a t a h a s b een p u shed ont o th e st ack an d in cr em ent ed be fo re da ta is pop ped f r om t he sta c k (see f i gur e 9 ). si nce th e st a c k is 25 6 byt e s d e e p , t h e 8 most sig- nif i ca nt b i t s ar e fo rced b y ha rd wa re . fo llowing an mc u re se t , or a f t e r a r e set stack pointer instruc - tio n (rsp), th e sta c k point e r co nt ains its re se t val- u e ( t h e sp7 to sp 0 bit s ar e se t) wh ic h is th e s t a ck high er a ddr ess. the le ast signif i can t byt e of t h e st ack po int e r (called s) can be dir e ctly accesse d by a ld in- st ru ct i o n. not e : w h en the lower limit is exceed ed , t h e st ack po int e r wr aps ar oun d to th e st ack u p p e r limit , wit h- out in dicat i ng t he sta c k o verf l ow. th e pr eviously st or ed inf o r m at io n is t h en over wr it te n a nd t her e- fo re lo st . the st ack also wrap s in ca se of an u nde r- flo w . the sta c k is used t o save t he re tu rn ad dr ess du r- ing a su bro u t i ne ca ll a n d t h e cpu cont ext dur ing a n in ter r u p t. th e us er m a y als o dir e c tly m a nip u l at e th e st ack by m ean s o f t he push an d pop inst ruc- tio n s. in t h e case of a n in te rr up t, t h e pcl is st or ed a t the f i r st loc a t i on p o in te d t o by th e sp . the n th e ot her r egist er s ar e st or ed in t h e n e xt locat i on s as sh own in figu re 9 . ? wh e n an in te rr up t is r e ceiv ed , th e sp is de cr e- m ent ed and t h e con t e xt is p u shed o n t he sta c k. ? o n re tu rn f r o m int e r r u p t, th e sp is inc r e m en te d an d th e co nt ext is po p p e d fr om t h e s t a ck. a subr ou tin e ca ll o c cup i es t w o locat i on s an d an in- te rr upt fiv e lo ca tio n s in the stack area. figure 9 . sta ck ma nip u lation exa m ple 15 8 00 00 00 01 70 sp 7 sp6 s p5 sp 4 sp3 s p2 sp 1 sp0 pch pcl sp pch pcl sp pc l pch x a cc pch pc l sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event pu s h y p op y i r e t ret or rsp @ 01ff h @ 0100h stac k higher addres s = 01ffh stac k lower address = 0100h 1 st72324jx st72324kx 23/164 6 supply, reset an d clock m a nagement the device inc l udes a ran ge of utility features for se cu rin g th e ap plicat ion in crit ical si tu at ions (f or examp l e in case of a p o wer br own- ou t) , an d r e - d u c in g th e nu m b e r of e x te r n a l co m p on en ts . a n over vie w is sho w n in figu re 11 . for mor e de ta ils, r e f e r t o d edicat e d par am et ric se ct i o n . mai n fe at ures opt i on al pll fo r m u lt iplying t h e f r eq ue ncy b y 2 (not to be used with internal rc oscillator in ord e r t o r e spect t h e m a x. op er at ing f r e que ncy) re se t seq uen ce m ana ger (rsm) multi-os cillator c l oc k management (mo) ? 5 crys tal/ceramic res o nator osc illator s ? 1 internal rc oscillator s yst em i n t e grit y management (s i) ? m ain sup p ly low vo lta ge d e t e ctio n (l vd) ? a uxiliary voltage detect or (avd) with interrupt c a pability for monitoring the main suppl y 6.1 phase lock ed loop if th e clock f r e q u ency in pu t t o t he pll is in t h e ran g e 2 to 4 mhz, t h e pll can be used t o m u lt iply th e f r eq uen cy b y t w o to obt ain an f os c2 o f 4 t o 8 mhz. the pll is en ab led b y o p t i on byte . i f th e pll is disab l ed, th en f osc2 = f osc /2 . ca ution: the pll is no t r e com m end ed fo r ap pli- c a t i on s wh er e tim i ng a c c u r a c y is re q u ir ed . ca uti o n : th e pll m u st no t b e u s ed w i th th e int e r - nal rc oscillator. figure 10. pll block diagram figure 1 1 . clock , rese t and sup p ly block diagr a m 0 1 p l l op t i on b i t pll x 2 f osc2 / 2 f osc low voltage detector (lvd) f os c 2 auxiliary voltage detector (avd) mu l t i - oscillator (mo) osc1 reset v ss v dd reset sequence manager (rsm) osc2 main cl ock a v d i nt e rr up t re qu es t c ontr o ll er pl l sy ste m in tegr i t y man a gem e nt wat chdog sics r time r (wdg ) wi th r e al t i m e cl ock (mcc /r tc) avd avd lvd rf ie wd g rf f os c (o pt io n) 0 f f cpu 0 0 0 1 st72324jx st72324kx 24/164 6. 2 m u lti -o sc illator (m o) the main clo c k o f t h e st7 ca n be ge ner at ed by th re e d i f f e re nt so ur ce type s comin g f r o m th e mu lti- osc illator bloc k: an ext e r nal sour ce 4 c r y s tal or ceramic resonator oscillator s an internal high frequency rc os cillator e a ch os cillator is optimized for a giv e n frequency ra nge in t e rm s of con s u m pt ion a nd is select able th ro ugh th e o pt i on byte . the asso cia t e d h ard ware configurat ion s ar e sho w n in t able 5 . re fe r to th e elect r ical char act e r i st ics section for more details. ca ution: the o s c1 a nd/ or osc2 pins must n o t be l e f t u n con nect ed. fo r t h e pu rp oses of fa ilure mod e an d eff e ct analysis, it sh ould be no t ed t h a t if th e osc1 and /o r osc2 pin s ar e lef t u n conn ecte d, the s t 7 main oscillator may start and, in this con- fig u r a t i on, could ge ner at e a n f osc clock f r equ ency in exce ss of t h e allo wed maximu m ( > 16m hz. ) , put t i ng t h e st7 in an u n saf e / und ef ine d st at e. the p r o d u c t b e h a vio ur m u st th er ef or e be c o n sid er e d und ef ine d whe n t h e o s c pins a r e lef t un co nn ect- ed. ex te rnal cloc k sourc e i n th is ex te rn al clo ck m o de , a clo ck s i gn al ( squ a r e , sin u s or t r ia ng le) with ~50% dut y cycle has t o dr ive th e osc1 pin while t he osc2 pin is tie d to g r ou nd . cr yst al /ce r ami c osc i l l a t o rs this family of osc illators has the advan tage of pro- ducing a ve ry accur a t e r a t e o n t h e ma in clock of the s t 7. the s e lection w i th in a list of 4 os cillators wit h dif f e r e n t f r eq uen cy r a n ges h a s t o b e do ne by opt ion byt e in o r d e r to re duce con s u m pt ion (r ef er to sectio n 1 4 . 1 o n p age 15 0 fo r m o re de ta ils o n th e f r equ ency ra ng es). i n t h is m ode of t h e mu lti- osc illator, the resonator and the load capacitors have t o be p l aced as clo s e as po ssibl e t o t he oscil- lat o r pin s in or de r to m i nimize out p u t dist or tio n and s t art-up stabilization ti me. the loading c a pac i- ta nce value s m u st b e adj uste d accord ing t o t h e s e lected oscillator. thes e osc illators are not stopped during the r eset phase to avoid losing time in the oscillator s t a r t- u p ph as e. inte rna l rc os ci lla to r this osc illator allows a lo w cost solution for the main clock o f the st7 using o n ly a n int e r nal re sis- tor and capaci tor. internal rc os cillator mode has th e dr awba ck of a lower fr eq uen cy a c cur a cy and sh ould n o t b e used in a pplicat io ns t h a t re qu ire ac- c u r a te tim i n g . in this mode, the two osc illa tor pins have to be tied to g r o und . i n o r d e r no t to ex ce ed t he m a x . op er a t in g fr eq u e n - c y, the internal rc os cillato r must not be us ed with th e pl l. tabl e 5. st7 cloc k sourc es har d w a r e configur ation external cloc k cry s tal/ceramic r esona tors internal r c oscillator osc1 osc2 external st7 source osc1 osc2 loa d capa cito rs st7 c l2 c l1 osc1 osc2 st7 1 st72324jx st72324kx 25/164 6.3 r eset sequen c e ma nager (rsm) 6. 3. 1 in tro duct i on the r e set se que nce man a g e r in clu des th re e re- s e t sources as show n in figu re 13 : external reset source puls e in te rna l lvd reset ( l o w volt ag e de te ct io n) internal w a tchd og re set these sources act on the reset p i n and it is al- wa ys ke pt low d u r i ng t he de lay pha se . the reset ser v ice r out ine vect or is f i xed at ad- dr esse s fff eh -f fffh in the st7 m e mo ry m ap. the b a sic reset seq uen ce con s i s t s o f 3 ph ases a s sh ow n in figu re 12 : act i ve ph ase de pen ding o n t he reset sou r ce 256 or 4 0 9 6 cpu clock cycle de lay (sele c t e d by o p tio n by te ) r eset vector fetch the 2 56 or 409 6 cpu clo ck cycle de lay allows t h e osc illator to s t abilis e an d ens u res that recov e ry has t a ken p l ace f r o m t h e reset st at e. th e sho r t e r or longer c l oc k cycle delay s h ould be s e lect ed by option byte to correspond to the stabilization time of the external osc illator used in the applic ation. the reset vect or f e t ch pha se d u r a t i on is 2 clock c ycles. fig u re 12 . reset se quen ce phas es 6. 3. 2 as ync h rono us ext e rna l reset pin the reset pin is bo th a n inp u t and an op en -dr a in out pu t with int e gra t e d r on weak pull- up r e sist or . this pu ll-up has n o f i xe d value but var i es in ac- co rda n ce wit h th e in put volt a ge. i t can be pu lle d low by ext e rn al circu i tr y to re se t t h e de vice. see e l ec tric al ch ar ac te rist ic s e ction for more details . a r eset signal originating from an external so urce mu st h a ve a d u r a t i on of a t least t h(rstl)in in ord e r t o b e r e cogn ized (see figu re 14 ). t h is de - te ct ion is asynchronous and therefore the mcu can enter reset state even in halt mode. figure 13. res e t block diagra m reset active phase int e rnal re set 2 56 or 4096 clock c y cle s fe tc h vector reset r on v dd wat chd og r e set lvd r eset int e rnal rese t pulse generat o r filter 1 st72324jx st72324kx 26/164 r eset sequen c e ma nager ( c ont ?d) the reset p i n is a n asyn ch ro nou s sign al wh ich plays a m a jor r o le in ems pe rf or man c e . i n a noisy envir onm ent , it is recom m en ded to f o llo w t h e guid e line s ment io ned in t he e l ectr ical char act e r i s- t i cs section. 6.3.3 external power-on r eset if t h e lvd is d i sable d by o p t i on b y te , t o st ar t up t h e microcon t r olle r cor r e c t l y, t h e user m u st e n sure by mea n s of an ext e r nal r e set circuit t h a t th e r e set s i gnal is held low until v dd is ove r th e min i m u m level s p ecified for the selec t ed f os c f r e que ncy. a pr ope r r e set sign al f o r a slo w r i sing v dd supply ca n gen er ally b e pr ovide d by a n exte rn al rc ne t- work connected to the reset pin. 6. 3. 4 i n te rna l l o w vol t age de te cto r (l vd) r eset two d i ff er en t reset sequ en ce s caused b y t he in- te rna l lvd circuit r y can be distin guishe d : pow e r-on rese t voltage drop r eset the device reset pin a c ts as an ou tp ut t hat is pulled low when v dd st72324jx st72324kx 28/164 s ystem integrity mana gement ( c ont ?d) 6. 4. 2 au xi li ar y vo l t a g e d e t e ct or (avd ) the vo lt age de te ct or f unct i on (avd) is ba se d on an an alo g co mpa r ison b e t w een a v it-(avd) and v it+(avd) r e fe re nc e v a lu e an d th e v dd ma in sup- ply. th e v it- reference value fo r falling v o ltage is lower than the v it+ r e f e r ence va lue fo r r i sing vo lt- age in or der t o avoid pa rasit i c de te ct ion ( h yst e r e - s i s). the ou tp ut of t h e avd co mpar at or is dir e ct ly re ad- able by t h e ap plicat ion sof t war e th ro ugh a rea l t i me st at us b i t ( avdf ) in the sics r regis t er. this bit is re ad on ly. ca uti o n : the avd fu nctio n is a c tive only if t h e lvd is e nab led th rou g h th e op tio n b y t e ( s ee sec- tio n 14. 1 o n pag e 150 ). 6. 4. 2. 1 moni t o ri ng the v dd main supply the avd volt ag e t h r e sho l d va lue is relative to the se lecte d lvd t h r e shold co nf igur ed by opt ion byte (see if th e avd int e r r upt is en ab led, an in te rr upt is g en- er at ed whe n t he volt ag e crosses th e v it + ( av d ) or v it-( av d ) th re sh old ( a vdf bit to ggle s ). in t h e ca se of a dr op i n vo lt age , t h e avd int e r r u p t acts a s an e a r l y wa rn ing, a llowing so ft war e t o sh ut down saf e ly b e f o re t he l v d r e set s th e micro c o n - troller. see figu re 16 . the int e r r u p t on t h e rising e dge is used t o inf o rm th e app lica t io n t hat th e v dd warning state is over. if t he vo lta ge rise t i me t rv is le ss t h a n 25 6 o r 4 096 c p u cycles (depending on t h e res e t delay selec t - ed by option by te), no avd interrupt will be gener- at ed when v it+(avd) is r e ac he d. if t rv is g r e a t e r t h a n 256 o r 40 96 cycle s t hen : ? if t he avd int e r r upt is en able d be fo re t h e v it+(avd) th re sh old is r e ac he d, t h e n 2 avd int e r - ru pt s w i ll be r e ceiv ed : th e firs t w h e n th e avdi e b i t is se t, and t h e se co nd whe n th e th re sh old is re ac he d. ? i f t he avd in te rr upt is e nab led af t e r th e v it+(avd) t h resho l d is re ache d t h en on ly one avd in te rr upt will occur. figure 1 6 . using t h e avd to mo nit o r v dd v dd v it+(avd) v it-(avd) avdf bit 0 0 reset value if avdie bit = 1 v hyst avd interr upt reques t int e rru pt pr oces s interrupt process v it+( lv d) v it-(lvd) lvd reset early w a rning in terrupt ( p ower h a s dro p p ed, mcu no t no t y e t in re se t) 1 1 t rv vo l ta g e ri se t i m e 1 st72324jx st72324kx 29/164 s ystem integrity mana gement ( c ont ?d ) 6. 4. 3 l o w pow e r mod es 6. 4. 3. 1 in te rrupt s the avd in t e rr up t even t g ene ra te s an int e rr up t if the avdie bit is set and the interrupt mask in the cc register is reset (rim instruction). mode d esc ription wa i t no e f fect on si. avd interrupt c aus e s the device to exit from w a it mode. h alt the cr sr register is frozen. interrupt e vent event flag enable contr o l bit exit fr om wait exit fr om halt a v d event avdf a v d ie yes n o 1 st72324jx st72324kx 30/164 system integrity mana gement ( c ont ?d) 6. 4. 4 re gi st er desc rip t i o n s ystem integrity (si) con t rol/status r egister (sic sr) re ad / w r i te re se t valu e: 0 00 x 00 0x ( 00 h) bi t 7 = reser v ed, must b e ke pt cle a re d. bi t 6 = avdie volt age de te ct or int e rr up t en ab le this b i t is set an d cle a re d by sof t wa re. it e nab les an in t e rr up t t o be g ene ra te d whe n t h e avdf f l ag ch ang es (t og gles) . th e pe ndin g int e r r u p t inf o r m a- tio n is au to mat i cally clea re d wh en sof t war e en te rs the av d interrupt routine. 0: avd in t e rr up t disab l ed 1: avd in t e rr up t en able d bi t 5 = avdf vo lta ge det e ct or f l ag this re ad- on ly b i t is set an d clear ed by har dwar e. i f t h e avd ie b i t is se t, an in te rr up t r e qu es t is ge n - er at ed wh en th e avdf b i t ch ang es valu e. ref e r to figu re 16 an d t o sectio n 6 . 4. 2. 1 f o r a ddit i on al de- tails . 0: v dd ove r v it+( a v d ) th re sh old 1: v dd un de r v it-(avd) threshold bi t 4 = lvdrf lvd r e set fla g this bit ind i ca te s t h at th e last re se t wa s g ene ra t- ed by t h e lvd b l ock. i t is set b y har dwar e (lvd r e - se t) an d clea re d by sof t w a r e (writ i ng zer o ). see wdgrf fla g d e scr i pt ion f o r mor e det ails. when th e lvd is disab l ed by opti on byt e , t he lvdrf bit valu e is u nde fin ed. b i ts 3:1 = re se rv ed , mu st be kept cleared. bi t 0 = wdgrf wa tchd og r eset f l a g this bit indic a tes that the last r e s e t was generat- ed b y th e wa tchd og per iph e ra l. it is set b y har d- wa re (wat chdo g r e set ) a nd cle a re d b y sof t w a r e (writ i ng zer o ) o r an lvd re se t (t o en su re a st able c l ea r e d st at e of th e wdg r f f l ag wh e n cpu st ar ts ) . co mbin ed wit h t h e lvdrf f l ag inf o rm at ion, t h e fla g descrip tio n is give n by t h e f o llo wing t able . app l ica t ion not es the lvdrf fla g is no t clea red wh en an ot her re- set t y p e occurs (e xt er na l or wa tchd og) , t h e lvdrf f l ag re main s set t o keep t r a c e o f t he or igi- nal f a ilur e . i n th is c a s e , a wa tc hd og r e se t c a n b e de te ct ed b y so ft war e wh ile an ext e r nal r e set ca n not . c aution: wh en th e l v d is no t activat e d wit h t h e a ss o c i at ed o p t i on b yte , th e wdg r f fla g ca n no t be used in t h e app lica t io n. 70 0 avd ie av d f lvd rf 000 wdg rf reset sources lv drf wdg r f external reset pin 0 0 watchdog 0 1 lvd 1 x 1 st72324jx st72324kx 31/164 7 inte rrupts 7. 1 introduct i o n the st7 en han ce d int er r up t ma nag eme nt pr o- vid e s t h e fo llowing f eat u r es: ha rdwa re int e rr upt s s o f t wa re in te rr up t (t rap ) ne st ed or concur re nt int e rr upt ma nag eme n t w i th flexible interrup t pr ior i t y and le ve l mana ge ment : ? u p to 4 sof t war e pr og ra mmab l e ne st ing levels ? u p to 1 6 int e r r up t vect ors f i xe d by h a r d war e ? 2 no n maskable e v e n t s : reset, tra p this int e r r up t ma nag eme n t is ba se d on: ? bit 5 a nd bit 3 of t h e cpu cc reg i ste r (i 1: 0) , ? in te rr u p t so ftw ar e pr io rity re g i ste r s ( i sprx ) , ? fixed in te rr upt ve ct o r add re sses locat e d a t t he high a ddr esses o f t h e me mor y m ap (f fe0h t o ffffh ) sor t e d by h a r d war e prio rity o r d e r . this e nha nced int e rr upt con t rolle r gu ara n t e e s fu ll upward compatibility with th e standard (not nest- ed) st7 int e r r up t con t r o lle r. 7.2 mask ing a nd processing flow the in te rr up t ma sking is man a g ed by t he i 1 an d i0 bit s of th e cc r egist er and t he isprx reg i ste r s wh ich give th e int e r r u p t so ftware priority level of each int e r r u p t vecto r (see tab l e 6 ). t he pro cess- ing f l ow i s shown in fig u r e 17 wh en an in te rr up t re qu est ha s t o be ser v i c e d : ? norm al pr ocessin g is suspe nde d at t h e end o f t h e cu rr ent inst ruct ion e x e c u t io n. ? the pc, x, a an d cc re gist ers ar e sa ved on to the s t ack. ? i 1 a n d i0 bit s of cc re giste r a r e se t acco rd ing t o t h e cor r e s p o n d ing valu es in t he isprx r egist er s of th e se rvic ed in te rr u p t ve cto r . ? t he pc is th en load ed wit h t he int e rr up t ve ct o r o f t h e int e rr upt t o ser vice an d t h e fir st instr u ct ion o f t h e int e r r up t ser v ice r out ine is f e t c h ed ( r ef er to ? i nt er rup t ma pp ing? t a b l e f o r vect or a ddr esses). the int e r r u p t ser v ice ro ut ine shou ld end wit h t h e iret instr u ct ion which causes th e co nt en ts of t h e sa ve d re giste r s to b e re co ve re d fr om t he st ack. not e : as a con s e que nce o f t h e iret in st r u ctio n, the i1 and i0 bits will be restored from the s t ack and the program in the pr evious level will resume. table 6. in te rrupt so ft war e pr ior i t y lev e ls figure 1 7 . int e rru pt proc ess in g f l o w cha r t interrupt softwar e priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable ) 1 1 ?iret? r est ore pc , x, a , c c s tac k pc, x, a, c c l o ad i1:0 from interrupt sw reg. fetch next reset tr a p pen ding ins t ruc tion i1 :0 f rom st ack load pc f r om in te r r u p t ve c t or y n y n y n inter r u p t ha s t h e s a me or a lo wer so ftwa r e pr io rit y th e i n ter rupt st ays pending than current on e i n te rr up t h as a h i g h e r so ftwa r e p r io r it y th an cu rr en t o ne execute instruction inte rrup t 1 st72324jx st72324kx 32/164 interr upts (con t?d ) se rvicing pen d ing int e r r upt s as sever a l int e r r up ts can be p e n d ing a t t he same t i me , the in te rr up t t o b e ta ke n in to a cco u n t is d e t e r - mine d by t h e f o l l owing t w o - st ep pr ocess: ? t h e high est sof t w are pr ior i ty int e r r u p t is ser v ice d , ? if several interr up ts ha ve t h e s a m e so ft war e p r i- orit y t hen th e in te rr upt with t he h i ghe st h a rd ware p r ior i ty is se r v ice d fir s t. figu re 18 describ es t h is decision p r oce s s. figure 1 8 . priorit y de cision proce s s wh en an in te rr upt re que st is no t serviced imm edi- at ely, it is lat c hed and t h e n pr ocesse d when it s s o ftware priority combined w i th th e ha r d wa r e pr i- or ity becom es t h e h i ghe st on e. no te 1 : th e har dwar e p r io rit y is exclusive while th e so ft ware o ne is no t. t h is allo ws th e p r e v io us pr ocess t o su cce ed with o n ly o n e in te rr upt . no te 2 : reset an d t r ap ca n b e con s id er ed as having th e hig h e s t sof t war e p r ior i t y in th e de cision pr ocess. di f f er ent i n t e rru pt vec t or sou r ces two int e r r upt sou r ce t y pes a r e man age d b y t h e st 7 int e r r u p t co nt ro ller: t he n on- maskabl e type (reset , t r ap) and t he m a ska b le type (e xt e r na l or f r o m int e r nal pe rip her als). no n-ma sk abl e sourc e s the s e so ur ce s ar e pr ocessed re gar dle s s o f t h e st at e o f t h e i1 a n d i 0 b i ts of t he cc r e g i st er (see figu re 1 7 ). after stacking the pc, x, a and cc registers (except for r eset), the co rresponding ve ct or is loa ded in t h e pc re giste r and th e i 1 and i 0 b i ts of t h e c c a r e se t t o d i sa ble in te rr up ts ( l ev el 3). the s e sou r ces allo w t he pr ocessor t o exit halt m ode . tr ap ( n o n ma sk ab le so ftw ar e in te rr up t) this software interrupt is s e rviced when the trap instruction is executed. it will be serv iced ac cord- ing t o th e flo w ch art in figu re 1 7 . reset the reset sour ce has t h e h i ghe st pr iori ty in t h e st 7. th is me ans t h a t t he f i rst cur r e n t r out ine h a s th e hig hest so ft war e pr ior i ty ( l evel 3) and th e hig h - est ha rd wa re p r ior i t y . s e e t h e re set ch ap te r fo r mo r e de ta ils. mask abl e sour ces mask able int e rrupt vect or sources can be serv iced if t h e cor r e s p ond ing int e r r up t is ena bled an d if it s own in t e rr up t so f t war e pr iorit y ( i n isprx re gist ers) is h i ghe r th an t h e on e cur r e n t l y bein g ser v ice d ( i 1 and i 0 in cc re giste r ) . i f a n y of th ese t w o con d i- tio n s is f a lse, t h e int e r r u p t is la tche d a nd t hus r e - mains pe ndin g . exte rn a l in te rr u p t s ext e r nal int e r r u p t s allo w t he pr ocessor t o exit f r om halt low po we r mode . ext e r nal int e r r up t se nsitiv- ity is software selec t able th ro ugh t h e ext e r nal i n - te rr upt co nt ro l r e g i st er (ei c r) . e x ternal interrupt triggered on edge w ill be latched and t h e in te rr upt re que st aut om at ica lly clear ed upo n ent er ing t h e in t e rr up t ser v ice r out ine . if sever a l in put p i ns of a gro up co nne cte d t o t h e sa me in te rr upt lin e ar e sele ct ed simult an eou sly, these w ill be logically ored. pe rip her al i n t e rr up ts usua lly t he pe riph er al int e rr up ts ca use th e mcu to exit f r o m halt m ode e x ce pt t h o s e ment ion e d in th e ? i n t err u p t map p ing ? ta ble. a per iph e r a l in te r- r u pt occ u r s wh e n a sp ec ific f l ag is se t in th e pe - riph er al sta t us re giste r s an d if t he cor r e s pon ding ena ble bit is set in th e per iph e r a l co nt ro l r e g i st er . the ge ner al se que nce fo r cle a rin g an int e r r u p t is based on a n access to th e sta t u s r e g i st er f o llowed by a r e a d or writ e t o an a s sociat ed reg i st e r . not e : t he cle a r i ng se que nce rese ts t h e int e r n a l latch. a pending interrupt (i.e. waiting for being serviced) will theref ore be lost if the clear se- quence is executed. p e n di ng software different interrupts same high est h a rdwa re p r iority s e rv ic ed pr io rity h i g h es t sof t ware p r iority s e rv ic ed 1 st72324jx st72324kx 33/164 interr upts (con t?d ) 7.3 interru pts an d low power modes al l in t e rr up ts allo w t h e pr ocesso r t o e x it t he wai t low po we r m ode . o n t h e cont ra ry, on ly e x t e rna l and ot her sp ecif ied in te rr upt s allow t he p r oce s sor t o exit fr om t h e h a lt m o de s (se e co lum n ?e xit fr om halt? in ? i nt er rup t ma ppin g ? t a b l e) . when s e v e r a l pe n d in g int e r r u p t s ar e pr es en t wh ile e x it - ing halt mod e , t h e fir s t on e se rviced can on ly be an interrupt with ex it from h a lt mode capability a n d it is s e le ct ed t h r o ug h th e sa m e d e c i sion pr oc - ess shown in fig u r e 18 . no te : if an in ter r u p t, t h a t is no t a b l e t o ex it fr om hal t mod e , is pe ndin g wit h t h e high est pr iorit y wh en exit ing halt mod e , t h is in t e rr up t is ser v iced af te r t he f i rst o ne ser v iced . 7.4 c o n curr ent & nested mana gemen t the following f i gu re 19 and f i gu r e 20 show tw o dif f e r e n t int e r r up t man age men t m ode s. th e f i rst is ca lled con c u r r ent mo de an d do es not allo w a n in- te rr upt to b e int e r r up te d, unlike t he ne st ed m ode in figur e 20 . t he int e rr up t har dwar e p r io rit y is given in t h is or der f r om th e lowest t o th e h i gh est: main, i t 4, it 3 , it 2, it 1 , it 0. t h e so ftw ar e pr io rity is g i v- e n fo r ea ch in te rr u p t. wa r n i n g : a s t a ck ov er flo w m a y o cc u r w i th ou t no - tif ying t he sof t w a r e o f t he f a ilur e . figure 1 9 . conc urre nt inte rrup t man a geme nt figure 2 0 . nes t e d int e rr upt ma nage ment main it4 it2 it1 trap it 1 main it 0 i1 hard ware priority softw are 3 3 3 3 3 3/ 0 3 11 11 11 11 11 11 / 1 0 11 rim it2 it1 it4 trap it3 it0 it3 i0 10 priority level used stack = 10 bytes main it2 trap main it 0 it2 it1 it4 trap it3 it0 hardware priority 3 2 1 3 3 3/ 0 3 11 00 01 11 11 11 rim it1 it4 it 4 it1 it2 it 3 i1 i0 11 / 1 0 10 softw are priority level used stack = 20 by tes 1 st72324jx st72324kx 34/164 interr upts (con t?d ) 7.5 interru pt register des crip t ion c p u c c r e gister interr upt bits re ad / w r i te re se t valu e: 1 11 x 10 10 ( x ah) bi t 5, 3 = i1 , i0 so ftw ar e in te rru p t p r io rity the s e t w o bit s in dicat e t he cur r en t in te rr upt sof t - wa re p r io rit y . the s e two b i ts ar e set / c le ar ed b y h a r d war e when ent er ing in int e r r upt . the load ed valu e is given by th e cor r espo nd ing b i ts in t he in te rr up t sof t w a r e p r i- orit y regist ers (isp rx). the y can be also se t/ clear ed by sof t war e wit h t h e r i m , si m, hal t , wfi, iret a n d pus h /po p in - st r u ctio ns ( see ? i n t e r r upt de dicat e d i n st ru ct ion s e t? t a b l e) . *note : tr ap and reset even ts can i n terrupt a level 3 pr ogr am. interrupt software priority regis- ter s (ispr x) r e a d / wr ite ( b it 7: 4 of isp r 3 a r e r ead o n ly) re se t valu e: 1 111 1 1 1 1 (ff h ) these f o u r re giste r s con t ain t he int e r r u p t sof t w a r e prio rit y o f ea ch int e rr up t vect or. ? e a ch interrupt vector (except r eset and trap) h a s co rr espon din g bit s in t hese r egist er s whe r e i t s own so ft war e pr iori ty is st or ed . t h is co rr e- sp ond ance is sh own in th e fo llowing t a b l e. ? ea ch i 1 _ x a n d i0 _x b i t va lu e in th e isprx r e g i s- ter s h a s th e s a m e m e a n in g as th e i 1 a n d i0 b i ts i n th e cc re giste r . ? le ve l 0 can n o t be writ t en (i 1_ x=1 , i 0_x=0) . i n t h is ca se , t he pr eviou s ly st or ed value is kep t . (ex- a m ple : p r eviou s=cfh, writ e=64 h, r e sult =44h ) the reset , an d trap vecto r s have no sof t w a r e p r ior i tie s. wh en o n e is se rvic ed , th e i1 a n d i0 b i ts of t h e cc r e g i st er ar e bot h set . caution : i f t h e i1 _x and i0 _x bit s a r e m odif i ed wh ile t h e int e r r u p t x is execut ed th e f o llo wing b e - haviou r h a s t o be co nsider ed : if t h e int e r r u p t x is s t ill pendi ng (new interrupt or flag not cleared) and th e ne w so ft war e p r io rit y is high er th an th e p r evi- ous on e, t he in te rr up t x is re -e nt ere d . ot he rwise, th e sof t war e pr ior i t y st ays u n chan ged up t o t h e n e xt in te rr up t re q u e st ( a ft er th e ire t o f the int e r - rupt x). 70 11 i1 h i0 nzc interr upt softw a r e priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable*) 1 1 70 i spr0 i1_3 i0_3 i 1_ 2 i 0_ 2 i 1 _ 1 i 0_ 1 i 1 _ 0 i 0_ 0 i spr 1 i 1_ 7 i 0 _ 7 i 1_ 6 i 0_ 6 i 1 _ 5 i 0_ 5 i 1 _ 4 i 0_ 4 is p r 2 i 1_ 11 i0 _1 1 i 1_ 10 i0 _1 0 i 1_ 9 i 0 _ 9 i 1_ 8 i 0 _ 8 is p r 3 1 1 1 1 i 1_ 13 i0 _1 3 i 1_ 12 i0 _1 2 vector address isprx bits f ffb h-fffah i 1_0 and i0_0 bits* fff9h-fff8h i 1_1 a nd i0_1 bits .. . . .. f f e 1h-ffe0h i1_13 a nd i0_13 bits 1 st72324jx st72324kx 35/164 interr upts (con t?d ) table 7. dedica ted int e rru pt inst ruc t ion set note : during the execution of an interrupt routine, the halt, popcc, rim, si m and wfi instructions change the current software priority up to the next iret instructi on or one of the previously mentioned instructions. instruction new descripti on function/e x ample i 1 h i0 n z c halt entering h a lt mode 1 0 ir et interru p t routine return pop c c, a, x, pc i1 h i 0 n z c jrm j um p if i1:0=11 (lev el 3) i1:0=11? jrnm j u m p if i1:0<>11 i 1:0<>11? pop cc pop cc from the stack m em => cc i1 h i 0 n z c rim e nable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim d isable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nm i 1 1 wfi w ai t for i n ter r up t 1 0 1 st72324jx st72324kx 36/164 interr upts (con t?d ) table 8. inte rrupt mapp ing notes: 1. in flash devices onl y a r eset or mcc/rtc interrupt can be us ed to wake-up from a c tive halt mode. 7.6 ex ter nal interr upts 7 . 6 . 1 i /o port i n t e rrupt sens it iv ity t h e ex te rn al inte r r u p t se ns itivity is controlled by th e i p a, ipb an d i s xx bit s o f t h e ei cr r e g i st er ( fig u r e 21 ). this c o ntrol allows to have up to 4 fully inde pen de nt ext e r nal int e r r u p t sou r ce sensit ivit ies. ea ch ext e r nal int e rr up t so urce ca n b e ge ne rat e d on f our (o r five) dif f e r e n t e v e n t s o n th e pin: falling edge rising e dge falling and rising edge falling edge and low level rising ed ge an d high le ve l ( only fo r ei0 an d e i 2) to g u a r an te e co rr ect fu nct i ona lity, t he se nsit ivit y bit s in t h e ei cr r egist er can be mo dif i ed o n ly wh en t he i1 a nd i 0 b i t s of t h e cc r egist er a r e bo th s e t t o 1 ( l ev el 3) . t h is m e an s th at in te rr up ts m u st be disab l ed b e f o re ch ang ing sensit ivity. the pen din g in te rr upt s ar e clea re d b y wr it ing a dif - ferent value in the isx[1:0], ipa or ipb bits of the eicr. n source block description register label priority or d e r exit fr om ha l t / active halt 1) addr ess vector res e t r eset n/a y e s fffe h - ffffh trap software interrupt no fffch-fffdh 0 n ot used fffah-fffbh 1 m c c /rt c m a in clock c ontroller time base interrupt mccs r higher priority y e s f f f 8h-fff9h 2 e i0 external interrupt port a3..0 n/a y e s f f f 6h-fff7h 3 e i1 external interrupt port f2..0 y es ff f4h-fff5h 4 e i2 external interrupt port b3..0 y es ff f2h-fff3h 5 e i3 external interrupt port b7..4 y es ff f0h-fff1h 6 n ot used ffee h -ffefh 7 s pi sp i p e ripheral interrupts spics r y es ffech-ffedh 8 t imer a t imer a peripheral interrupts t a s r n o ffeah-ffebh 9 t imer b t imer b peripheral interrupts t b s r n o ffe8h-ffe9h 10 s ci s c i peripheral interrupts s cisr low e r priority no ffe6h-ffe7h 11 avd auxiliary voltage detec tor interrupt sicsr no ffe4h-ffe5h 1 st72324jx st72324kx 37/164 figure 21. external interrupt control bits is10 is11 eicr sensitivity control pbor.3 pbdd r .3 ipb bit pb3 ei2 interrupt source p ort b [3:0] in ter rupt s pb3 pb 2 pb1 pb0 is10 is11 ei c r sensitivity control pbor.4 pb ddr.4 pb4 ei3 interrupt source port b 4 inte rrup t is20 is21 eicr sensitivity control paor.3 padd r .3 ipa bit pa3 ei0 interrupt source p ort a3 in terr u pt is20 is21 ei c r sensitivity control pfor.2 pf ddr.2 pf2 ei1 interrupt source port f [2 :0 ] inte rrup ts pf2 pf 1 pf0 1 st72324jx st72324kx 38/164 interr upts (con t?d ) 7.7 ex ter nal interr upt control r e gister (eicr ) re ad / w r i te re se t valu e: 0 0 0 0 000 0 (0 0h) bi t 7: 6 = i s 1[ 1: 0] e i 2 and e i 3 sensit ivit y the in te rr upt sensit ivit y, d e f i ned u s i ng t he i s 1[ 1: 0] bit s , is ap plie d to t h e f o llowing ext e r nal int e r r upt s: - ei2 ( por t b3 .. 0) - ei3 ( por t b4 ) the s e 2 bit s can b e writ t en o n ly wh en i 1 an d i 0 of th e cc re giste r ar e bo th set to 1 (leve l 3 ) . bi t 5 = ipb in te rr up t po lar i ty fo r po rt b this bit is used to inv e rt the sens itivity of the port b [3 :0 ] ext e r nal in te rr upt s. i t can b e set a nd clea red by sof t w a r e on ly when i 1 an d i 0 of t h e cc r e g i st er ar e bot h set t o 1 ( l evel 3) . 0: no sens itivity invers ion 1: sensitivity inversion bit 4: 3 = i s 2[ 1: 0] ei0 and e i 1 se nsit ivit y the in te rr upt se nsit ivit y, de f i ned u s in g t he i s 2[ 1: 0] b i ts , is a p p lied t o th e fo llow i n g e x te rn a l in te rr up ts: - ei0 ( por t a3 .. 0) - ei1 ( por t f2 . . 0 ) these 2 bit s can b e writ t en on ly whe n i 1 an d i0 of th e cc re giste r ar e bo th set to 1 ( l evel 3) . bi t 2 = ipa in te rr up t po la rity fo r po rt a this b i t is used t o in ve rt t h e sensit ivity o f th e por t a [3 :0 ] ext e r nal int e rr upt s. i t can b e se t a nd clear ed by sof t w a r e on ly when i 1 and i 0 of t h e cc r egist er are b o t h set t o 1 ( l evel 3) . 0: no sensitivity invers ion 1: sensitivity inversion bit s 1 : 0 = rese rved, must a l wa ys b e ke pt clea re d. 70 is11 is10 ipb i s21 i s20 i pa 0 0 is11 is10 exter n al int e rr upt sensit ivi t y ipb bit = 0 ipb bit =1 00 falling ed ge & low lev e l rising edge & high lev e l 0 1 r i sing edge only f alling edge only 1 0 falling edg e only r ising edge only 1 1 rising and falling edge is11 i s 10 exter n al int e rr upt sensit ivi t y 0 0 fallin g edge & low level 0 1 ris i ng edge only 1 0 falling edge only 1 1 rising and falling edge is21 is20 ext e rnal i n ter r u pt s e nsiti v it y ipa bit =0 ipa bit =1 00 falling edge & low l e vel risin g edge & high lev e l 0 1 r i sing e dge only f alling edge only 1 0 falling edge only r is ing edge o n ly 1 1 rising and falling edge i s 21 is20 ext e rnal i n ter r u pt s e nsiti v it y 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge 1 st72324jx st72324kx 39/164 interr upts (con t?d ) tabl e 9. nest ed i n te rrup t s regi st er ma p and res e t val u e s addr ess (hex.) register label 76543 210 0024h ispr0 reset value ei1 e i0 mcc + si i1_3 1 i0_3 1 i1_ 2 1 i0_2 1 i1_1 1 i0_1 111 0025h ispr1 re s e t v a lu e sp i e i3 ei2 i1_7 1 i0_7 1 i1_ 6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0026h ispr2 re s e t v a lu e avd sci t im er b t ime r a i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0027h ispr3 r e s e t v a l u e 1111 i1_13 1 i0_13 1 i1_ 1 2 1 i0_12 1 0028h ei c r re s e t v a lu e is11 0 is10 0 ipb 0 is21 0 is20 0 ipa 000 1 st72324jx st72324kx 40/164 8 power saving modes 8. 1 introduct i o n to give a large measure of flex ibility to the applica- tio n in t e r m s of power consum pt ion, f our main p o w e r s a v i ng m o de s ar e imp l e m en te d in th e st 7 (see f i gur e 22 ) : s l o w , wait ( s l o w wait) , ac - ti ve halt and halt . af t e r a reset t h e nor mal o per at ing m ode is se- lecte d b y de fa ult ( r un mo de) . this m ode d r ives th e d e vice ( c pu a nd emb edd ed pe rip her als) by mea n s of a mast er clo c k which is based on t h e main oscillator frequenc y di v i ded or multiplied by 2 (f osc2 ). fro m run mo de , t h e dif f e re nt po we r saving modes may be selec t ed by set t i ng th e r e le va nt register bits or by callin g the spec i f ic st7 software instruction whose action depends on the oscillator st at us. figure 2 2 . power saving mo de tra n sition s 8. 2 sl ow m o de this m ode h a s two t a r get s: ? to re duce po we r co nsump t io n by d e crea sing th e i n t e rn al clock in t he de vice , ? to ad apt t he int e r n a l clock f r equ ency (f cpu ) t o t h e availab l e su pp ly volt age . sl ow mo de is con t r o lle d b y t h r e e bit s in t h e mccsr re giste r : t h e sms bit which e nab les or disable s slow m ode a nd t w o cpx bit s which select th e int e r nal slow f r equ ency (f cpu ). i n th is m o de , th e m a s t er c l oc k f r e q u e n c y ( f osc2 ) ca n be divide d by 2, 4 , 8 or 16. th e cpu a nd p e - riph er als a r e clocked at t h is lower f r e q u ency (f cpu ). not e : sl ow-wai t m ode is activat e d wh en en te r- ing th e wai t mo de while th e d e vice is a l re ady in sl ow mode . figure 23. slow mode clock transitions power consumption wait slow run ac t i ve halt high low slow wait halt 00 01 sm s cp 1 : 0 f cpu ne w slow n ormal run mod e mccsr fr eque ncy r e que st re ques t f os c2 f osc2 /2 f osc2 /4 f osc2 1 st72324jx st72324kx 41/164 p o we r sa ving modes ( c ont ?d) 8. 3 wai t mode wai t m ode pla c e s t he mcu in a low p o wer con- su mpt i on m ode b y sto p p i ng t he cpu. this power s a ving mode is selec t ed by calling the ?w fi? instruc t ion. a l l peripherals remain activ e . during wait mode, th e i [ 1 : 0 ] b i ts of t he cc re giste r a r e f o r c ed t o ?1 0?, to en able al l int e r r u p t s . all ot her r egist er s and memo ry re main uncha nge d. the mcu r e main s in wai t mode u n t il an in te rr upt or reset occurs, wh er eup on th e pr og ra m cou nt er br anch es t o t he st ar t i ng add re ss o f t he int e r r u p t or reset se rvice ro ut ine. the mcu will remain in wa it mode until a reset or a n in te rr upt occurs, ca using it t o wake up . re fe r t o figu re 2 4 . fig u re 24 . wait mo de flow- c ha rt not e : 1. before serv icing an inte rr u p t, th e cc re gis t e r is pushe d on t he sta c k. t he i [ 1 : 0 ] bit s o f t he cc re g- is te r ar e se t t o the c u r r e n t s o ftware priori ty level of th e int e r r u p t r o u t in e and reco ve red wh en t h e cc reg i st e r is po pp ed. wfi instruction reset interrupt y n n y cp u o s ci l l a t o r periphera ls i[1:0] bits on on 10 off fetc h r es et vec tor o r se rvice i nterrupt cpu oscil l a t o r periphera ls i[1:0] bits on off 10 on cp u o s ci l l a t o r periphera ls i[1:0] bits on on xx 1) on 2 5 6 o r 4096 cpu c lo ck cycle d elay 1 st72324jx st72324kx 42/164 p o we r sa ving modes ( c ont ?d) 8.4 active-halt and halt modes acti ve-halt an d hal t m ode s ar e t he t w o lo w- est power con s u m pt ion mo des o f th e mcu. th ey ar e bot h en te re d by e x ecut ing t he ?halt? inst ru c- t i on . t h e de cisio n to en te r eit h e r in act i ve-h a lt or hal t m ode is g i ve n b y t he mcc/ rtc int e r r u p t ena ble f l ag ( o i e b i t in mccsr r egist er ). 8. 4. 1 acti ve-halt mode a c tive-halt mode is the lowest power con- su mpt i on mo de of t h e mcu with a r eal tim e clock availab l e. i t is en te red b y execut ing th e ?halt ? in- st r u ctio n wh en t he oi e b i t of t h e m a in clock con- troller status regis t er (mccsr ) is set (see section 10. 2 on pag e 5 6 f o r m o re de ta ils on t he mccsr re giste r ) . t h e m cu ca n ex it act i ve- hal t m o de o n r e ce p - t i on o f e i th er an m c c / rt c in te rr up t, a specific in- te rr upt (see ta ble 8 , ?i nt er ru pt m app ing , ? on pag e 36 ) or a reset. wh en exit ing acti ve- hal t mo de b y mea n s of an int e r r u p t , no 256 or 409 6 cpu cycle dela y occu rs. the cpu resu mes ope ra tio n by ser v icin g t he in te rr up t o r b y f e t c hing th e re se t vecto r which woke it up ( see fig u re 26 ). wh en ent e ring acti ve- h al t mo de , th e i [ 1 : 0 ] bit s in t he cc reg i ste r ar e f o r c e d t o ?1 0b? t o e nab le in- te rr upt s. the r ef or e, if an int e r r up t is p e n d ing , t h e mcu wakes u p imme diat ely. in active-h a lt mode, on ly the main oscillator and it s a s socia t e d co unt er (mcc/rtc) a r e r un- ning to ke ep a wa ke -u p tim e ba se . all ot h e r p e r i ph- er als ar e n o t clo c ke d excep t t h o s e which g e t t heir clo c k su pply f r om ano th er clock ge ner at or ( s u c h as ex ternal or aux iliary osc illator). the saf egu ar d a g a i nst st ayin g lo cked in acti ve- h a lt mode is provided by the os cillator interrupt. no te: a s s o on as the interrupt capability of one of the osc illators is selected (mcc sr.oie bit set), ent er ing act i ve- hal t mo de wh ile t h e wat c h dog is act i ve doe s no t ge ne rat e a reset . this me ans t h a t th e d e vice cann ot spen d m o re th an a de f i ned d e lay in t h is p o wer saving m ode . c aution: wh en ex itin g ac ti ve-h a l t m o de fo l- lowing an int e rr up t, o i e b i t of mccsr r e g i st er must no t be clear ed be f o re t delay a f te r th e in te r- ru pt occur s (t delay = 256 o r 409 6 t cpu d e lay de- pen ding on opt io n byt e ) . o t her wise , t h e st7 e n - te rs halt mo de f o r th e rem a inin g t de l a y per iod . fig u re 25 . active- halt timing ove r view fig u re 26 . active- halt mo de flow- c ha rt not e s : 1. this delay occurs only if the mcu exits active- h alt mode by means of a r eset. 2. pe rip her al clocke d with an e x t e r n a l clock so ur ce c a n s t ill be active. 3. only the mcc/rtc inte rr up t a n d s o m e sp ec ific int e rr up ts can exit th e mcu f r o m act i ve- halt mode ( such a s ext e r nal int e r r u p t ) . re fe r to t a b l e 8 , ?i nt er ru p t m a pp in g, ? on p a g e 3 6 f o r mo re det ails. 4. before serv icing an inte rr u p t, th e cc re gis t e r is pushe d on t he sta c k. t he i [ 1 : 0 ] bit s o f t he cc re g- is te r ar e se t t o the c u r r e n t s o ftware priori ty level of th e in te rr upt r o u t in e a nd rest or ed wh en th e cc reg i st e r is po pp ed. mccsr oie b it p o wer saving mode entered when halt instru ction is executed 0 h alt mode 1 active-h alt mode ha lt run run 256 or 4096 cpu cycle delay 1) reset or inter rupt ha lt in struction fe tch vector act i v e [mccs r.oie=1] hal t instr uct ion res e t in ter rupt 3) y n n y cp u os cilla tor pe riphe r al s 2) i[1 :0] b its on off 10 off fe tch r ese t vec tor or s e rv ic e i n ter rupt cpu oscillator peripherals i[1 :0] b its on off xx 4) on cp u os cilla tor pe ripheral s i[1 :0] b its on on xx 4) on 2 5 6o r 4 0 9 6c p u c l o c k c y cl e d el ay (mccsr.oie=1) 1 st72324jx st72324kx 43/164 p o we r sa ving modes ( c ont ?d) 8. 4. 2 halt mo de the halt mode is the lo we st po we r co ns um p t io n m o de o f th e m cu. it is e n t e r e d b y ex ec ut ing th e ?hal t? instr u ct ion whe n t he oi e bit of th e main c l oc k controller status register (mccsr ) is c l ea re d (s ee sectio n 10 .2 on pa ge 5 6 f o r mo re de- tails on the mc csr regis t er). the mcu can e x it halt mo de on r e cept ion o f ei- th er a sp ecif ic in te rr upt (se e tab l e 8, ?i nt er ru pt m a pp in g, ? on pa g e 36 ) or a r eset. when exiting hal t mode by m ean s of a reset o r an in te rr upt , the os cillator is immedi ately turned on and the 256 or 4096 cpu c ycle delay is used to stabilize the osc illator. afte r the start up delay, the c p u re su mes op era t io n by ser v icing th e int e rr upt or by fe tchin g t he r e set ve ct o r which woke it u p (see fig- ur e 28 ). wh en e n t e r i ng halt mode , t h e i [ 1 : 0 ] b i ts in t h e cc r e g i st er ar e fo rced to ?10 b ?t o e n a b le int e rr up ts. the r ef or e, if an in te rr up t is pe ndin g , th e mcu wa ke s up immed i at ely. in halt mode, the main oscillator is turned off ca using a ll in te rn al pr ocessi ng t o be st opp ed, in- clu d ing t h e op er at ion of t h e on -chip p e rip h e r als. al l p e r i phe ra ls a r e n o t clo c ked exce pt th e on es wh ich g e t t h e i r clo c k su pply fr om an ot her clock generator (s uc h as an ex ternal or auxiliary oscilla- to r) . the compatibility of wa tchdog operation with hal t mod e is co nf igur ed b y t h e ?wdghalt? op- t i on bit of t h e op tio n b yt e . t h e h a lt in str u c t io n wh en execu t e d wh ile th e wa tch dog syst e m is en- able d , can gen er at e a wat c h dog reset (see se ctio n 14. 1 on pag e 150 ) f o r mo re d e t a ils. figure 2 7 . halt tim i ng over view fig u re 28 . halt mode flow-c hart not e s : 1 . wdg h al t is a n op tio n bit . se e op tio n byt e se c- tio n fo r mor e de ta ils. 2. pe rip her al clocke d with an e x t e r n a l clock so ur ce c a n s t ill be active. 3. only some specif ic int e rr up ts can exit th e mcu fr om halt mo de ( such as ext e r nal in te rr upt ) . re- fe r t o t a b l e 8 , ? i nt er ru pt m a p p in g,? o n pa g e 36 fo r mor e det ails. 4. before serv icing an inte rr u p t, th e cc re gis t e r is pushe d on t he sta c k. t he i [ 1 : 0 ] bit s o f t he cc re g- is te r ar e se t t o the c u r r e n t s o ftware priori ty level of th e int e r r u p t r o u t in e and reco ve red wh en t h e cc reg i st e r is po pp ed. halt run run 256 or 4096 cpu c ycle d e lay reset or inter rupt ha lt in struction fetch vector [mccs r.oie=0] ha l t instruction re set interr upt 3) y n n y cp u o s ci l l a t o r periphera ls 2) i[1:0] bits off off 10 off fetc h r es et vec tor o r se rvice i nterrupt cpu oscill a t o r periphera ls i[1:0] bits on off xx 4) on cp u o scil l a t o r periphera ls i[1:0] bits on on xx 4) on 256 or 4096 c pu clock de lay watchdog enable disable wd g h a l t 1) 0 watchdog reset 1 (mccsr.oie=0) cycl e 1 st72324jx st72324kx 44/164 p o we r sa ving modes ( c ont ?d) 8. 4. 2. 1 hal t mode rec o mmend ati o n s ? make sur e t hat an ext e r nal even t is availab l e to w a k e up t h e m i cr oc on tr olle r fr om h a lt m o d e . ? whe n u s in g an ext e rn al in te rr upt t o wake up t h e microcontroller, reinitia lize t h e co rr es po nd in g i/ o as ? i npu t pull- up wit h i n t e r r up t? bef or e exe c u t in g th e halt instr u ct ion. th e main reas on for this is th at t he i/ o may b e wr on gly conf igu r e d d ue t o e x - te rn al int e r f e r en ce or by an u n f o r e seen lo gical co ndit i on . ? for the s a me reason, reinitialize the lev e l sens i - tiven e ss of ea ch e x t e r n a l in te rr up t as a pr ecau- tio nar y me asur e. ? th e op co de f o r th e halt inst ru ct ion is 0 x 8 e . to a v oid an u nexp e cte d hal t in str u ctio n du e to a program counter failure, it is ad vis e d to c l ea r all o c cu rr ences o f t h e da ta value 0x8e f r o m me mo- r y . fo r examp l e, avoid de fin i ng a con s t a n t in rom with the value 0x8e. ? as t h e hal t instr u ct ion clea rs t he int e rr upt mask in t h e c c r e g i st er to a llo w in te rr up ts , t h e u s e r m a y ch oose t o cle a r a ll pen ding in te rr up t bit s b e - f o re execut ing t h e halt in st ru ctio n. this avo i ds e n t e r i ng o t h e r p e rip h e r al int e r r upt ro ut ines af te r e x ecut ing t he e x t e r nal in te rr upt ro ut ine cor r e - sp ond ing to t he wa ke -up even t (r eset or ext e r nal in te r r u p t ) . 1 st72324jx st72324kx 45/164 9 i/o ports 9. 1 introduct i o n the i / o por t s of f e r d i ff er en t f unct i ona l mode s: ? t r ansf e r of dat a th rou g h digit a l inpu ts an d o u t put s and f o r sp ecific pin s : ? e x te rn a l in te rr up t ge ne r a t i on ? alt e r n a t e sign al inp u t / o u t put fo r t he on -chip p e - riph er als. an i / o po r t co nt ains u p t o 8 pin s . each p i n can be pr og r a m m ed ind epe nde nt ly as d i git a l in put ( with or wit h o u t in t e rr u p t gen er a t io n) o r digit a l o u t put . 9. 2 fu nc ti on a l de s c ri p t i o n e a ch port has 2 main registers: ? dat a re gist er ( d r) ? data d i rection regis t er (dd r ) and o ne o p t i ona l r e g i st er : ? op tio n re gis t er ( o r) ea ch i / o pin may be pr ogr amm ed u s ing t h e corr e- s p o n d in g r e gist er bit s in th e dd r a n d or re gis - te rs: bit x co rr espon ding t o pin x of t h e po rt . the sa me cor r espo nd ence is u s e d f o r t h e dr r e g i st er . the f o llowing de scr i pt ion ta ke s int o acco unt t h e or re gist er, ( f or sp ecific p o r t s which d o n o t pr o- v i de th is re gis te r re fe r to th e i/ o po rt i m p l e m e n ta - tion se ct ion ) . the ge ne ric i / o block d i agr am is sh own in figu re 2 9 9. 2. 1 in put mo des the inpu t con f ig ur at ion is sele ct ed by cle a r i ng t h e co rr espo ndin g ddr r e g i st er bit . in t h is ca se , r ead ing t he dr r egist er r e t u r n s t h e digit a l valu e app lied t o t he ext e r nal i / o p i n. dif f e r ent in put m ode s ca n b e sele ct ed by sof t w are th ro ugh t h e o r r egist er . no tes : 1. writ ing t he dr r egist er mo dif i es t he lat c h value but doe s n o t a f f e ct t h e pin sta t u s . 2 . wh en sw itch in g fro m in pu t to ou tp u t m o de , th e dr r egist er h a s t o be wr itt e n f i rst t o d r ive t h e co r- re ct l e vel on t he pin a s soon a s t he po rt i s co nf ig- ur ed as an ou tp ut . 3. do not use read/modify /write instructions (bset o r bres) t o mo d i fy th e d r r e gist er ex te rnal i n te rrupt fun c ti on wh en a n i/ o is con f igur ed a s i npu t wit h in te rr upt , an e v e n t on t h is i / o ca n ge ne rat e a n ext e r nal in te r- ru pt r equ est t o t he cpu. ea ch p i n ca n inde pen den tly gen er at e an int e r r u p t r e qu es t. t h e in te rr up t se ns itivity is independently p r og ra m m a b l e usin g th e s e n sit ivity bit s in th e ei cr r egist er . ea ch exte rn al int e r r up t vect or is linked t o a de di- ca te d gr oup o f i / o po rt p i ns (see p i nou t d e scr i pt ion and int e r r u p t sect ion) . if seve ral inpu t pin s are se- lecte d sim u lt ane ou sly as interrupt sources, thes e are f i rst d e t e cte d a cco rdin g to t he sensit ivit y b i ts in th e ei cr r e g i st er a n d t h e n logicall y ored . the ext e r nal in te rr upt s a r e h a rd ware in t e rr up ts, wh ich me an s th at t h e r e q uest la tch (n ot a cce ssible dire ct ly by t h e ap plicat i on) is au to mat i cally clear ed wh en t he cor r e s p ond ing in te rr upt vecto r is fe tche d. to clea r an un wa nt ed pe nd ing int e r r u p t by sof t w are , t h e se nsitivit y b i ts in t h e ei cr r egist er m u st be m o dif i ed . 9. 2. 2 out put m odes the ou tp ut conf igu r a t io n is se lecte d b y se t t in g t h e co rr espon din g ddr re giste r b i t. i n t h is ca se , writ - ing t he dr re giste r ap plies th is dig i ta l valu e to t h e i/ o p i n t h ro ugh th e lat ch. the n r ead ing t h e dr re g- ist e r r e t u r n s th e pr eviously st or ed valu e. two dif f e r e n t out pu t m ode s can be sele ct ed by so ft war e th ro ugh th e or re gist er: ou tp ut push- pu ll and o pen -d ra in. dr re giste r value a nd ou tp ut pin sta t u s : 9. 2. 3 al t e rna t e fu nct i o n s w h e n a n on -c hip p e r ip he ra l is co n f ig ur ed t o us e a pin, th e alt e r nat e f u n c t i on is au to mat i cally sele ct - e d . th is a l te rn at e fu nc tio n ta ke s pr ior i ty o ve r th e st an dar d i / o p ro g ra mmin g . wh en th e sign al is comin g f r om a n o n - c h i p p e rip h - era l , th e i / o pin is aut om at ica lly co nf igu r ed in out - put mode ( p u s h - p u ll or op en dr ain a c cor d in g to t h e peripheral). wh en th e sign al is goin g t o an on -chip pe riph er al, th e i / o pin must be conf igu r e d in inpu t mode . in th is case, t h e pin sta t e i s also dig i ta lly r ead ab le by a d d r e s sin g th e dr re gis t e r . not e : i npu t p u ll- up con f igur at ion ca n cause u nex- pect ed va lue a t th e inp u t of t h e alt e r nat e p e r i phe ra l inpu t. wh en an o n - c h i p per iph e r a l use a pin as in- put an d ou tp ut , t h is pin has t o be co nf igur ed in in- put flo a t i ng mo de. dr push-pull o pen-dr ain 0v ss vss 1v dd floating 1 st72324jx st72324kx 46/164 i/ o ports (con t?d ) figure 29 . i/o port g e ne ra l bloc k dia g ram ta ble 1 0 . i/o p o rt m o de o p tions lege nd : n i - not imple m en te d o f f - imple m en te d no t act i va te d o n - imple m en te d an d activat e d note : the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the de- vice against positive stress. configuration m ode pull-up p -buffer d i odes to v dd to v ss input floating with/witho ut interrupt o f f off on on pull-up w i th/without interru p t o n o u tput push-pull of f on open d r ain (logic le vel) off true open drain ni n i n i (see note) dr ddr or data bus pad v dd alternate enable al terna te output 1 0 or sel ddr sel dr sel pull-up condition p-b u ffer (see tab l e belo w) n-b u ffer pull-up (see table below) 1 0 analog input if implem ented alternate input v dd diodes (see table below) external source (ei x ) in terr upt cm o s sch m itt trigger register access 1 st72324jx st72324kx 47/164 i/ o ports (con t?d ) table 11 . i/o po rt conf ig urat ions no tes : 1. when t h e i / o po rt is in in put con f ig ur at ion an d t h e associat ed alt e r n a t e f u n c t i on is en ab led as an o u t put , reading the dr register will read the alternate func tion output status. 2. when t h e i / o po rt is in o u t put con f igur at ion an d t h e a s sociat ed alt e rna t e f u n c t i on is e nab led as an in put , the alternate function reads the pin status given by the dr register content. hardwar e configuration input 1) open-drain o u tput 2) pus h -pull o utput 2) condition pad v dd r pu external interrupt d ata b u s pul l - u p interrupt dr re giste r a cc ess w r source (ei x ) dr register condition alternate input not implemented in true open drain i/o ports analog input pad r pu data b u s dr d r r e gist er a cces s r/w v dd alternate al ter na te enable output reg i s ter not implemented in true open drain i/o ports pad r pu data b u s dr d r r e gist er a cces s r/w v dd alternate al ter na te ena ble o u tp ut reg i s ter not implemented in true open drain i/ o p o r ts 1 st72324jx st72324kx 48/164 i/ o ports (con t?d ) c aution : t he a l te rna t e f unct i on m u st n o t be a c - tivat e d as lon g as t he p i n is conf igu r e d as inp u t wit h int e r r up t, in or de r t o a v oid g e n e ra tin g spu r io us interrupts. an al og al te rnat e fu nct i o n wh en t h e p i n is used as an adc inpu t, t he i / o must be con f ig ur ed as f l oa tin g inpu t. the an alog multiplex e r (c ontrolled by the ad c registers ) swit ch es t h e an alog volt age pr esen t on th e se lect- ed p i n to th e commo n an alog rail which is co nn ect- ed t o th e adc inp u t . it is r e comme nde d no t t o ch ang e th e volt age le ve l or load ing on a n y po rt pin wh ile con v e r sion is in pr ogr ess. fu rt he rmo re it is r e com m en ded n o t to have clo c kin g p i ns locat e d close to a se lecte d an- alog p i n. w arn ing : the ana log in put volt age level must be with i n t he limit s st at ed in t he ab solut e ma xi- mum r a t i ngs. 9.3 i/o port implementa tion the ha rd wa re imp l eme nt at i on o n e ach i/ o po rt de- pen ds on t h e se tt ing s in t h e ddr and or reg i ste r s and sp ecific f eat u r e o f t h e i/ o p o rt such as adc i n - put or t r u e op en dr ain . switching th e s e i / o p o r t s f r om one st at e to a not h- er sho u ld b e do ne in a seq u e n ce th at pr event s un- wa nt ed sid e ef f e ct s. recomm end ed sa fe tr an si- tions are illus t rated in fig u r e 30 ot he r t r a ns i tio ns ar e po te nt ially risky a n d sh ould be a voide d, sin c e t h e y ar e like l y t o pr es en t un wa nt ed s i de -e ff ec ts su ch a s spu r iou s in te rr upt gen er at ion . fig u re 30 . i n t e rrup t i / o por t stat e tra n si t i on s 9. 4 low po wer modes 9. 5 interrupts t h e ex te rn al inte r r u p t e ven t ge n e r a t e s an in te rr up t if th e co rr espon ding con f ig ur at ion is select ed with ddr an d o r re gist ers and t he int e r r u p t ma sk in t h e c c r e g i st er is no t ac tive ( r im in st ru ctio n ) . mode description wa it no effec t on i/o ports. external interrupts cause th e device to exit from w a it mode. ha l t no effec t on i/o ports. external interrupts cause th e device to exit from halt mode. interrupt event event flag enable contr o l bit exit fr om wait exit fr om halt e x ternal inte rrupt on selec t ed external event - ddrx or x yes y es 01 f l o a t i ng /p ul l - up in te rru pt in put 00 floating (reset st a t e ) input 10 open-drain output 11 push-pull out p ut xx = ddr, or 1 st72324jx st72324kx 49/164 i/ o ports (con t?d ) 9. 5. 1 i/ o port impl eme n ta ti on t h e i/o p o r t r e gis t er co n f ig ur at ion s ar e su mm a - rised as follows. s t an dard ports p a 5: 4 , pc 7: 0, pd5 : 0, p e 1: 0, pf 7 : 6 , 4 i n t e rr u p t p o rt s p b 4, pb2 : 0, pf 1: 0 (w ith pull-up) p a3, pb 3, pf2 ( w it h out pull- up ) true open drain port s pa 7: 6 table 12 . port co nfigur ation mode d d r o r floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 mode d d r o r floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode d d r o r floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr floating input 0 open drain (high sink ports ) 1 p o rt pin name in put output or = 0 or = 1 o r = 0 o r = 1 port a pa7:6 floating t rue o pen-drain pa5:4 flo a ting pull-up open drain p u s h-pu ll pa3 flo ating flo ating interrupt open drain pu s h-pu ll port b pb3 flo ating flo ating interrupt open drain pu s h-pu ll pb4, pb2 :0 flo ating pull-up interrupt open drain pu s h-pu ll port c pc7:0 flo ating pull-up open drain pu s h-pu ll port d pd5:0 flo ating pull-up open drain pu s h-pu ll port e pe1:0 flo a ting pull-up open drain p u s h-pu ll port f pf7:6, 4 f lo ating pull-up open drain pu s h-pu ll pf2 f lo ating f lo ating interrupt open drain pu s h-pu ll pf1:0 f lo ating pull-up interrupt open drain p u s h-pu ll 1 st72324jx st72324kx 50/164 i/ o ports (con t?d ) tabl e 13 . i / o po rt regi st er ma p and rese t val u e s addr ess (hex.) register label 76543 210 reset value of all i/o por t register s 000 00 000 0000h p adr msb lsb 0001h p addr 0002h pa o r 0003h p bdr msb lsb 0004h p bddr 0005h pb o r 0006h p cdr msb lsb 0007h p cddr 0008h pc o r 0009h p ddr msb lsb 000ah p dddr 000bh pd o r 000ch pe d r msb lsb 000dh p e ddr 000eh pe o r 000fh pf d r msb lsb 0010h p f ddr 0011h pf o r 1 st72324jx st72324kx 51/164 10 on-chip peripherals 10.1 watc hdog timer (wdg) 10.1.1 int r oduc tion the wat c h d o g t i me r i s used to d e t e ct t he occu r- re nce of a so ft war e f ault , usually ge ner at ed b y e x - te rn al in t e rf er en ce o r by u n f o re seen lo gical co ndi- tio n s, which cau s e s t he app lica t ion pr ogr am to aba ndo n its n o r m al se que nce. t he wa tch dog cir- cu it g e n e ra te s an m c u r e set on expir y o f a pr o- gr amme d tim e per iod , un less t h e p r o g ra m re fr esh- es th e coun te r?s cont en ts be f o re th e t6 bit be- co mes cl e a r ed. 10. 1. 2 ma in fe at ures pr og ra mmab l e fr ee -r unn ing d owncoun te r pr og ra mmab l e re se t re se t ( i f wat chdo g act i va te d) wh en t he t 6 bit r e ac he s z e r o opt i on al re set o n halt inst ru ct ion (conf ig ura b le b y op tio n byte ) ha rdwa re wat chdo g se lecta b le b y op tio n byt e 10. 1. 3 fu nct i on al des c ri pt io n the cou n t e r valu e st or ed in t h e wat chdo g co nt ro l re giste r ( w dg cr bit s t[6 : 0] ), is d e crem ent ed ever y 163 84 f os c2 cy cles (approx. ), and the leng th o f th e time ou t per iod can be p r og ra mmed by t h e u ser in 64 increm ent s. if t h e wat chdo g is activat e d ( t he wdga bit is set ) and wh en t h e 7 - b i t t i mer (b its t[ 6: 0] ) r o lls over fr om 40 h t o 3fh (t6 b e come s clea re d) , it init iat e s a reset cyc le pulling low th e reset pin for typically 500 ns. the applic ation program mus t write in the w d g cr re gis te r a t re gu la r in te rv als du r i ng n o r m al o p e r a t i on to pr ev en t a n m c u re se t. t h is do wn - co unt er is fr ee -r unn ing: it co un ts do wn even if t h e wa tchd og is disab l ed. th e value to be st ore d in t h e wdgcr r e g i st er must b e bet ween ffh an d c0 h: ? the wdga bit is set ( w at ch dog e nab led ) ? t he t6 bit is set t o pre v e n t g ene ra tin g a n im me- d i at e re set ? the t[ 5: 0] b i ts cont ain th e nu mber of incre m en ts wh ich r e p r esen t s t he t i me de lay b e f o r e th e wa tchd og pr od uces a reset (see f i gur e 32 . ap- p r o x im at e time out du ra tio n ). the t i min g va rie s be twe e n a min i m u m an d a ma xim u m va lu e d u e t o th e u n known st at us o f th e p r escale r whe n writ - i ng t o th e wdg c r reg i ste r (see f i gur e 33 ). followin g a re se t , t h e wat chdo g is d i sa ble d . on ce activat e d it ca nn ot b e disab l ed, exce pt b y a r e set . the t6 bit ca n be u s e d t o gen er at e a sof t w a r e r e - se t ( t he wdga b i t is set a nd t h e t6 bit is clear ed) . i f th e wa tc hd og is ac tiva te d, t h e hal t in str u c t io n w ill generate a reset. figure 3 1 . wat c hd og bloc k diag ram reset wdg a 6-bit downcounter (cnt) f os c2 t6 t0 wdg prescaler watchdo g co ntr o l register (w dgcr) div 4 t1 t2 t3 t4 t5 12-bit m cc r t c co unter m sb lsb div 64 0 5 6 11 mcc/rtc tb[1: 0 ] bit s (m ccsr register) 1 st72324jx st72324kx 52/164 w a tchd og timer (c on t?d ) 10.1.4 how t o pr ogram t h e watc hdog timeo u t figu re 3 2 shows th e line a r rela t i onship bet ween th e 6- bit value to be lo ade d in t h e wa tchd og co un- te r ( c nt) an d t he r e sult ing t i meou t dur at ion in mil- lise c o nds. th is can be used fo r a quick calculat ion w i th ou t ta king t h e t i m i ng va r i at ion s in to a c c o u n t. if mor e pr ecision is n eed ed, u s e th e f o r m ula e in fig- u r e 33 . ca ution: when writ ing to th e wdgcr reg i st e r , al- wa ys writ e 1 in t h e t6 bit t o avoid g ene ra tin g an immed i at e re se t. figure 3 2 . appr oximat e time out dura tion cnt value (hex.) wa tc hdog t i me out ( m s) @ 8 m h z. f osc2 3f 00 38 128 1. 5 65 30 28 20 18 10 08 50 34 1 8 82 98 11 4 1 st72324jx st72324kx 53/164 w a tchd og timer (c on t?d ) figure 3 3 . exa c t t i me out dura tion (t mi n and t ma x ) wh e r e : t mi n0 = ( l sb + 12 8) x 64 x t osc2 t max 0 = 163 84 x t os c2 t os c2 = 125 ns if f osc2 =8 mh z cnt = va lue of t[ 5: 0] b i t s in t he wdg c r re gist er ( 6 bit s ) msb an d l sb ar e valu es f r o m t h e t able be low d epe ndin g o n t h e t i meb a se se lecte d b y th e t b [1 :0 ] bit s in the mccs r register to ca lc ula t e t h e minimum wat c hd og tim e out ( t min ): if then el se to ca lc ula t e t h e max i mu m wat c hdo g time out ( t max ): if then el se no te : in t h e abo ve f o r m u l ae, divisio n re su lts must b e ro und ed d o wn to t h e next in te ger va lue. exampl e: with 2ms timeout selected in mccsr register tb1 bit (mccsr reg.) tb0 bit (mcc sr r e g. ) selected mccsr timebase msb l sb 0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 2 0 3 5 1 1 25ms 4 9 5 4 v a lue of t[5:0] bits in wdg cr register (hex.) min. watchdog timeout (ms) t min max. watchdog timeout (ms) t ma x 00 1.496 2.048 3f 128 128.552 cnt ms b 4 ------------ - < t min t min 0 16384 c n t t osc2 + = t min t mi n0 16384 c n t 4c nt ms b ---------- ----- - - ? ?? ?? 192 l s b + () 64 4c nt ms b -- ---- ----- ---- - - + t osc2 + = cn t ms b 4 ------- ---- - - t ma x t ma x0 16384 c n t t osc2 + = t ma x t ma x0 16384 c n t 4cnt ms b ---- ----- ---- --- - ? ?? ?? 192 l s b + () 64 4cnt ms b ---- ----- ---- --- - + t osc2 + = 1 st72324jx st72324kx 54/164 w a tchd og timer (c on t?d ) 10. 1. 5 lo w po wer mo des 10.1.6 hard war e wa tc hdog op tion if ha rd wa re wat c hdo g is sele ct ed b y o p t i on byt e , th e wat c h dog is a l wa ys act i ve and th e wdg a b i t in th e wdgcr is not used. re fe r t o t h e o p t i on byte descript i on. 10. 1. 7 usi ng ha lt mode wi t h t h e wdg (wdgha lt option) the following recomme nda t i on app lies if halt mod e is used wh en t he wat c h d o g is en able d . ? bef o r e execut ing t h e halt in st ru ctio n, r e f r e s h th e wdg co unt er , t o a v o i d an une xp ect ed wdg rese t imme diat ely af t e r waking u p th e micro c o n - troller. 10. 1. 8 i n t e rrup t s no ne. 10. 1. 9 regi st er des c ri pti o n co nt ro l r e gi s t e r ( w dg cr ) re ad / w r i te re se t valu e: 0 111 1 1 1 1 (7f h ) bi t 7 = wdga activ a t i on b i t . this b i t is se t by so ft war e and o n ly clea re d by har dwar e a f t e r a re se t. whe n wdga = 1, t h e wa tchd og can g ene ra te a r e set . 0: wat chdo g disab l ed 1: wat chdo g en able d not e : th is b i t is not u s e d if t he har dwar e wat ch- dog o p t i on is ena bled b y op t i on byt e . bit 6: 0 = t[ 6: 0] 7-bit counter (msb to lsb). these bit s con t a i n t h e valu e o f t he wat c h dog co unt er . i t is d e cre m en te d ever y 16 384 f osc2 cy - cle s ( app ro x. ) . a r e set is p r o duced wh en it r o lls over f r o m 40h t o 3f h (t6 b e come s clea re d). m ode des c ription sl ow no e ffe ct o n wa tch d o g . wait no ef f e ct on wat chd og. ha l t oie bit in m ccsr register wdghalt bit in option byte 00 no w a tchdog reset is generated. the mcu enters halt m o de. the watch- dog counter is decrem e nted once and t hen stops c ounting and is no longer able to generate a watc hdog reset until the m cu receives an external inter- rupt or a reset. if an external interrupt is received, the w a tchdog re starts counting after 256 or 4096 cpu clocks . if a res e t is gener ated, the w a tchdog is disabled (rese t state) unless hard w a re watchdog is selected by option b y te. for applica- tion rec om m endations see section 10.1.7 below. 0 1 a reset is generated. 1x no reset is generated. the m cu e n te rs active halt mode. the watc hdog counter is not de cremente d . it stop c ounting. w h en the mcu receives an osc i llator interrupt or e x ternal inte rrupt, the w a tchdog restarts counting im- mediately. when the m cu rec e iv es a reset the watc hdog restarts counting af ter 256 or 4096 c p u clo cks. 70 wdg a t6 t5 t4 t3 t 2 t1 t0 1 st72324jx st72324kx 55/164 table 14 . wat c hd og tim e r re giste r map a nd re set va lu es addr ess (hex.) register label 76543 210 002ah wd g c r re s e t v a lu e wd ga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 1 st72324jx st72324kx 56/164 10. 2 main clock con t roller with rea l time clock and beep er (mcc/rtc) the main clock c o ntroller co nsist s of t h ree dif f e r - ent fu nct i ons: a p r og ra m m a b l e cpu clo ck pr es ca ler a clo c k- out sig nal t o supp ly ext e r nal de vice s a real time cloc k timer with i n terrupt capability ea ch fu nctio n can b e used in dep end en tly and si- mult an eou sly. 10. 2. 1 prog rammabl e cpu cl ock pre sca le r the pr og ram m ab le cpu clock pr esca ler supp lies t h e cloc k fo r th e st 7 cpu a n d its int e r n al pe rip h - er als. i t man age s slo w po we r sa ving mod e (see se ctio n 8. 2 slow mode fo r mor e de ta ils) . the presc a ler select s the f cpu main cl ock f r e q u en- cy an d is cont ro lled by th re e bit s in t h e mccsr r e g i st er : c p [1 :0 ] a n d sm s. 10. 2. 2 clock- out ca pabilit y the clock-out capability is an alternate function of an i/ o por t pin t hat o u t p u t s t h e f cp u c l oc k to driv e exte rn al d e vices. i t is cont r o lled b y t he mco bit in th e mccsr r e g i st er . c aution : wh en se lect ed, t h e clock out p i n sus- pen ds t h e clo c k dur ing acti ve- h alt mod e . 10. 2. 3 real time cloc k time r (rtc) the coun te r of t h e re al tim e clock t i mer a llows an int e rr up t t o be ge ner at ed b a sed on a n accu ra te rea l tim e clock. fo ur d i ff e r en t t i me bases de pen d- in g dir e ctly on f osc2 ar e availa ble. th e whole fu nctio nalit y is co nt ro lled b y f our b i ts of th e mcc- sr re gis t e r : tb[1 :0 ], oi e a n d o i f. wh en th e rtc int e rr up t is en able d ( o i e b i t se t) , th e st7 en te rs act i ve- halt mode wh en t h e halt inst ru ct ion is execut ed . se e se ct ion 8. 4 ac- tive-h alt and halt mode s fo r m o r e de ta ils. 10. 2. 4 beep er the bee p f unct i on is con t r o lle d b y t h e mccbcr reg i st e r . i t ca n out pu t t h r e e sele ct ab le f r eq ue ncies on the beep pin (i/o port alternate function). figure 3 4 . ma in clock cont roller (m cc/rt c ) bloc k diag ram div 2, 4, 8, 16 mcc/rt c i nt erru pt sms cp1 cp0 tb1 t b0 oie oif c p u clock mccsr 12-bit mcc rtc c o unt er to cpu and periphera ls f osc2 f cp u mco mc o bc1 bc0 mc cb cr beep selection beep signal 1 0 to wat c hd og ti mer div 64 1 st72324jx st72324kx 57/164 main c l ock controller w i th r e al time cloc k (con t?d ) 10. 2. 5 lo w po wer mo des 10. 2. 6 interrup t s the mcc/rtc in te rr up t event gen er at es a n in te r- ru pt if th e oi e b i t of th e mccsr re giste r is set and th e in te rr up t mask in th e cc r e g i st er is n o t act i ve (rim ins t ruction). no te : the mcc/rtc interrupt wakes up th e mcu f r o m acti ve-halt mo de, no t f r om halt mo de. 10. 2. 7 regi st er des c ri pt ion mcc control/status register (mc c sr) re ad / w r i te re se t valu e: 0 0 0 0 000 0 (0 0h ) bi t 7 = mc o main clock out selec t ion this b i t ena bles t h e mco al t e r nat e fu nctio n o n t h e p f 0 i / o po r t. it is se t an d cle a r e d by so ftw ar e. 0: mco alt e r n a t e fu nctio n disab l ed ( i /o pin f r ee f o r g ene ra l-pu rp ose i/ o ) 1: m c o a l te rn at e fu ncti on en able d (f cpu o n i/ o po r t ) no te : to re duce p o wer consum pt ion, t he mco f u n ct i on is no t ac tive in ac ti ve-h a l t mo d e . bit 6: 5 = cp[1 :0 ] c p u c loc k prescaler t h e se b i ts se le ct th e cp u cloc k pr es ca ler w h ic h is app lied in th e dif f e r ent slow mod e s. th eir actio n is co ndit i on ed by t h e set t in g o f th e sms bit . the s e two bit s a r e set and cle a re d by so ft war e bi t 4 = sms slow m ode sel e ct this b i t is se t an d cle a r ed b y sof t war e . 0: nor m al mo de. f cpu = f os c2 1 : slow m o de . f cpu is given by cp1, cp0 se e s e c t ion 8. 2 sl ow m o d e and sect ion 10 .2 main cloc k c o n t roller with r eal time c l ock and be eper (mcc /rtc) fo r mor e d e - tails . bit 3: 2 = t b [1 :0 ] tim e base cont r o l these b i t s sele ct t he p r og ra mmab le d i vid e r t i me base. the y ar e set a nd clea red b y sof t w a r e . a m odif i cat i on of th e t i me base is t a ken int o ac- co unt at t h e end of t he cu rr ent pe rio d ( p r e viously s e t ) t o av oid a n un wa nt ed time shift. this allows to use th is t i me ba se a s a r eal t i me clock. bi t 1 = oi e oscillator interrupt enable this b i t set and clea re d by so ft war e . 0: os cillator interrupt dis a bled 1: os cillator interrupt enabled this in te rr up t can be u s e d to e x it fr om active- halt m ode . w h en this bit is set, calling the st7 software h alt inst ruction enters the ac tive-h a lt pow e r saving mode . mode description wa i t no e f fect on mcc/rtc peripheral. mcc / rtc interrupt cause the device to ex it from wait m o de. a c tive- ha l t no e f fect on mcc/rtc counter (oie b i t is set), the registers are frozen. mcc / rtc interrupt cause the device to ex it from activ e-halt mode. ha l t mcc / rtc coun ter and registers are frozen. mcc / rtc operation resumes when the mcu is woken up by an interrupt with ?ex i t from halt? capability. interr upt e ven t event flag enable control bit exit fr om wait exit fr om halt time base ov erflow event oi f oi e y e s n o 1) 70 mco c p1 cp0 s m s tb1 t b0 oie o if f cp u in slow m ode cp1 cp0 f os c2 / 2 0 0 f os c2 / 4 0 1 f os c2 / 8 1 0 f os c2 / 16 1 1 counter prescaler time base tb1 t b0 f os c2 =4mh z f os c2 =8mhz 16000 4ms 2 ms 0 0 32000 8ms 4 ms 0 1 80000 20ms 10m s 1 0 200000 50ms 25m s 1 1 1 st72324jx st72324kx 58/164 main c l ock controller w i th r e al time cloc k (con t?d ) bi t 0 = oi f os cillator interrupt flag this bit is set by har dwar e an d clear ed by sof t w are re adin g t h e mccsr r e g i st er . it in dicat e s when set that the main os cillator has reached the selec t ed elap se d t i me (tb1 :0 ). 0 : tim e ou t no t re ac he d 1: t i meo u t r each e d c aution : t he bres and b set ins t ructions must n o t b e used on t h e m c csr r egist er t o avoid unin t e n t i on ally clea rin g th e oi f bit . mc c be ep control r e gister (mccbc r) re ad / w r i te r e s e t va lue : 00 0 0 00 00 ( 0 0h ) bit 7: 2 = reser v ed, must b e ke pt cle a re d. bit 1: 0 = bc[1:0] b e ep cont rol these 2 bits s e lect the pf1 pin beep capability . the be ep ou tp ut sign al is availa ble in active- halt mo de but has t o be disab l ed to r edu ce t h e co nsump t io n. table 15 . ma in clock cont roller regist er ma p a nd rese t values 70 00 00 0 0 b c 1 b c 0 bc1 b c 0 b eep m ode w i th f os c2 =8m h z 00 o f f 01 ~2 - k h z output beep signal ~50% duty cycle 10 ~ 1 - k h z 1 1 ~500-hz addr ess (hex.) register label 76543 210 002bh si c s r re s e t v a lu e 0 avdie 0 avdf 0 lv drf x0 0 0 wdg r f x 002ch m ccsr re s e t v a lu e mc o 0 cp1 0 cp0 0 sm s 0 tb1 0 tb0 0 oie 0 oi f 0 002dh m ccbcr r e s e t v a l u e 00000 0 bc1 0 bc0 0 1 st72324jx st72324kx 59/164 10. 3 16 -bi t tim e r 10.3.1 int r oduc tion the t i me r con s ist s o f a 16- bit fr ee -r unn ing co unt er d r iv en b y a pr og ra m m ab le p r e sca le r. it may be used f o r a va rie t y of p u rp oses, in clu d ing pulse leng th me asur emen t of up t o t w o in put sig- nals ( in put ca pt ur e ) o r ge ner at ion o f u p to t w o ou t- put wa ve f o rm s ( out pu t comp ar e and pwm ). pu lse len g t h s and wa vef o rm per iod s can be m od- ulated from a few mic r os econds to several milli- se co nds u s in g t h e tim e r pr esca ler and t he cpu clo c k pr esca ler . so me st7 devices have t w o on -chip 1 6 - b it tim e rs. the y a r e co mple te ly inde pen de nt , a nd do n o t sh ar e an y r e sou r ces. the y a r e synchr on ize d a f t e r a m cu r e s e t a s lo ng a s th e t i me r c l oc k fr eq ue n - cie s ar e no t mo dif i ed. this d e scr i pt ion cover s one o r t w o 16- bit t i mer s. in st 7 de vi ce s wit h t w o t i mer s , r egist er name s are pr ef ixe d wit h ta (t imer a) o r tb (tim er b) . 10. 3. 2 ma in fe at ures pr og ra mmab l e p r escale r: f cpu d i vid ed by 2, 4 or 8. overf l o w sta t u s f l ag a nd ma skab le int e r r up t ext e r nal clo c k in put ( m ust be at lea s t 4 t i mes slo w e r t han t h e cpu clock speed) w i th the choic e of a c t i ve edg e 1 or 2 o u t put co mpa r e f u n c t i on s ea ch wit h : ? 2 de dicat ed 16 -b it r egist er s ? 2 de dicat ed pr og ra mmab l e sig n a l s ? 2 de dicat ed sta t u s f l ag s ? 1 de dicat ed ma skab le int e r r u p t 1 o r 2 in pu t ca pt ur e fu nc tio n s ea ch w i th : ? 2 de dicat ed 16 -b it r egist er s ? 2 de dicat ed act i ve edg e se lectio n signa ls ? 2 de dicat ed sta t u s f l ag s ? 1 de dicat ed ma skab le int e r r u p t pu lse wid th m odu lat i on mo de ( p wm) o n e pu lse m o de re duced po we r mod e 5 alt e r nat e f u n c t i on s o n i / o por t s ( i cap1, icap2, ocmp1, oc mp2, extclk)* t h e blo ck d i ag ra m is sh ow n in f i gur e 35 . *note: so me tim e r p i ns m a y n o t be av aila b l e ( n o t bon ded ) in so me st7 devices. ref e r t o t he d e vice pin ou t d e scr i pt ion . wh en rea d in g a n in put sign al o n a no n- bon ded pin, the va lue will always be ?1?. 10. 3. 3 fun ct ion a l des c ri pt io n 10.3.3.1 count er the ma in blo c k of t h e pr og ra mmab le time r is a 16- bit f r e e run n in g u p coun t e r an d it s associat ed 16- bit r egist er s. t he 16- bit r egi st er s ar e m ade up of t w o 8- bit r e g i st er s calle d high & low. co unt er re giste r (cr): ? c o unt er high reg i ste r ( c hr) is t he mo st sig- nif i ca nt byte ( m s byt e ) . ? c o unt er l o w reg i st er ( c lr) is th e least sig- nif i ca nt byte ( l s byt e ) . a l te rn at e co un te r reg i st er ( a cr) ? a lte r na t e co unt er hig h regist er ( a chr) is t h e m o st sig n if ic an t by te (m s byte ) . ? a lte r na t e co unt er low regist er ( a cl r) is t h e le a st sign ific an t by te (l s b yte ). t h e se tw o r e a d - o nly 1 6 - b it r e gis t er s co nt ain th e s a m e v a lu e bu t with t h e d i ff er en ce t h a t re ad in g th e aclr reg i st e r d oes not clea r th e t o f b i t (t imer overf l o w fl ag) , locat e d in t h e st at us re giste r , ( s r) , (see n o t e at th e en d of par ag ra ph t i tle d 16 -b it r ead se que nce) . wr itin g in t he clr r e g i st er o r aclr r egist er r e set s th e fr ee r unn ing cou n t e r t o t he fff ch val ue. bo th co unter s h a ve a re set valu e of fffch ( t h i s is th e o n ly valu e which is re loa ded in th e 16- bit t i m- e r ). t h e r e s e t va lu e of b o t h co un te rs is als o fffch in on e pulse mod e and pwm mod e . the ti mer clock dep en ds on t he cl ock co nt ro l bit s of the c r2 regis t er, as illus t rated in t able 16 clock co nt ro l b i ts . t h e va lu e in the co u n te r r e gist er re - pea ts ever y 13 107 2, 2 621 44 or 524 288 cpu clock cycles d epe nd ing on t h e cc[ 1: 0] b i ts. the tim e r fr equ en cy can be f cpu /2 , f cp u /4 , f cpu /8 or an exte rna l fr equ en cy. ca ution: in flash de vices, timer a f u n ctio nalit y has the following restrictions: ? t a o c 2 hr an d t a oc 2l r re gis t e r s ar e wr ite on ly ? in pu t capt ur e 2 is n o t im plem ent ed ? the cor r e spon ding in te rr up ts ca nno t b e used (ic f 2 , oc f2 f o r ce d by h a r d w a r e to ze ro ) 1 st72324jx st72324kx 60/164 16- bit timer ( c ont ?d) figure 35. timer block diagram mcu-peripheral interface counter alterna te output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal b u s latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (control/status register) 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output co mpare r eg i st er 2 input capture re g i st e r 1 inp u t captur e register 2 cc[1:0] co unter pin pin pin pin pin register reg i ster no te : if ic, oc a n d to in ter r u p t re qu es ts ha ve s e p a r a te v e c t o r s t hen th e l a s t o r i s n o t pr es en t ( s e e de vi c e i n t e r r u p t ve ct o r ta bl e) (see note) cs r 1 st72324jx st72324kx 61/164 16- bit timer ( c ont ?d) 16- bi t re ad se que nce : (f r o m eit h e r t h e co unt er re giste r or th e alte rna t e co unt er re giste r ) . t h e us er m u s t r e a d th e ms byte f i rst , t h e n th e l s b y te va lu e is b u f f e r e d au to m a tica lly. this buffered v a lue rema ins u n chan ged u n t il t h e 16- bit r ead seq uen ce is comp let ed, e v e n if t h e user reads the ms byt e several times. af t e r a com p let e r ead ing sequ en ce , if o n ly t h e cl r re giste r or acl r re giste r ar e r e a d , t hey r e - t u r n th e ls byt e of t h e co u n t va lu e at th e tim e o f th e re ad. wh at ever t he time r mode use d ( i npu t ca pt ur e, ou t- put com par e, o ne pulse mod e or pwm mod e ) an over flo w occu rs whe n t h e cou n t e r ro lls over f r o m ffffh to 0 000 h th en: ? th e to f b i t o f th e s r r e g i st er is se t. ? a t i me r int e r r u p t is ge ner at ed if : ? t o i e b i t of th e cr1 r e gist er is se t a n d ? i bit of th e cc re giste r is clea re d. if one o f t hese cond itio ns is fa lse , t he int e r r u p t r e - main s p e n d ing t o be issu ed as soon as t h e y are bot h t r u e. cle a ri ng th e o v e r f l ow in t e rr up t re que st is d o n e in t w o st eps: 1. reading the s r register while the tof bit is s e t. 2. an access ( r e ad or wr it e) t o th e clr r e g i st er . not e s : the tof b i t is no t cl ear ed by acce sses to aclr r e g i st er . th e a d vant ag e o f acce ssin g t h e aclr r e g i st er ra th er t han th e clr r egist er is th at it a llows simult an eou s use o f th e o v e r f l ow f u n c t i on and re adin g t h e f r e e r unn ing co unt e r a t ran dom t i m e s (f or ex am p l e, to m e as ur e e l a p s e d tim e ) with - out th e risk o f clear ing t h e t o f bit er ron e o u sly. th e tim e r is n o t a ffe cte d b y w a it m o de . in halt mod e , t h e coun te r sto p s co un tin g un til t h e mode is exite d . coun tin g t h e n r e sume s f r om t h e pre v io us cou n t ( m cu awake ned by an int e r r u p t ) or fr om th e r e set coun t (mcu awake ned by a re se t) . 10. 3. 3. 2 ext e rn al cl ock the e x t e rna l clo c k ( w h e r e availa ble) is se lecte d if cc0=1 an d cc1 = 1 in t h e cr2 re gist er. the status of the exed g bit in the cr2 register det er mine s t h e t ype o f level t r a n sitio n on t h e exte r- nal clock pin extclk that w ill trigger the free run- ning cou n t e r . the counter is s ynchron iz ed with the falling edge of t h e in te rn al cpu clo c k. a minim u m of f o u r f a l ling edg es o f th e cpu clock must occu r bet ween t w o consecu t ive active edg es of th e e x t e r n a l clo c k; t hus t he exte rn al clock fr e- que ncy m u st b e less th an a qu art e r of t he cpu clo c k fr eq uen cy. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + ? t other instructions be ginn ing o f t he sequ en ce sequence completed l s by te ls byt e m s by te 1 st72324jx st72324kx 62/164 16- bit timer ( c ont ?d) figure 3 6 . coun ter timing dia g ram, int e rn al c l o ck di vi de d b y 2 figure 3 7 . coun ter timing dia g ram, int e rn al c l o ck di vi de d b y 4 figure 3 8 . coun ter timing dia g ram, int e rn al c l o ck di vi de d b y 8 note: the mcu is in reset state when the internal reset signal is high, when it is low the mcu is running. cpu c l ock fffd fffe ffff 0000 0001 0002 0003 internal reset tim er c l ock co unter register time r ov erflow flag (to f ) fffc fffd 0000 0001 cpu clock interna l rese t timer clock counter reg i ster tim e r overflow fla g (t of ) cpu clock internal reset timer clock c o unter reg i ster timer overflow flag (tof) fffc fffd 0000 1 st72324jx st72324kx 63/164 16- bit timer ( c ont ?d) 10.3.3.3 input ca ptu r e in t h is sectio n, t he in de x, i , ma y b e 1 or 2 becau se th er e ar e 2 inpu t cap t u r e f u n c t i on s in t h e 1 6 - b it tim e r. the t w o 16 -b it inp u t capt ur e re giste r s ( i c1 r and ic2r) ar e used t o lat c h t h e value o f th e fr ee r un- ning co un te r af t e r a t r a n sitio n is de te ct ed on t h e icap i pin ( s e e figu r e 5) . ic i r r e g i st er is a r ead -o nly r e g i st er . the active t r ansit ion is sof t w a r e pr ogr amm able t h r o u g h th e iedg i bit o f con t r o l regist er s (cr i ). timing r e solu tio n is on e co unt o f t he f r e e r u n n ing co unt er : ( f cpu / c c [1 :0 ]) . pr oce dure : to u se t h e inp u t capt ur e fu nctio n sele ct t h e f o llo w- ing in the cr2 register: ? se lec t t h e t i me r clo ck (cc [ 1 : 0 ] ) (se e ta ble 16 cl o c k co nt ro l b i t s ). ? sele ct t he e dge of th e act i ve tr an sit i on on t h e i c ap2 pin with th e i e dg 2 b i t (t he icap 2 p i n must be con f ig ure d as f l oat in g in put or inp u t with pull- up wit h o u t int e r r upt if this c o nfiguration is availab l e) . a n d select the following in the cr1 register: ? set th e ici e b i t t o gen er at e an in te rr upt af te r an inpu t cap t u r e co ming f r om ei th er t h e icap1 pin o r th e ica p 2 pin ? sele ct t he e dge of th e act i ve tr an sit i on on t h e icap1 p i n wit h th e i e dg1 bit ( t h e i c ap1 p in must be conf igu r e d as f l oa tin g inp u t o r inpu t wit h pull- up without interrupt if this configuration is availa- ble) . wh en an in pu t capt ur e occur s : ? i c f i b i t is se t. ? t he i c i r re giste r co nt ains t h e value of t h e fr ee r u n n ing coun te r o n t he active t r ansit ion on t h e icap i p i n (see f i gur e 40 ). ? a t i mer in te rr up t is ge ne rat e d if th e ici e bit is set an d t h e i b i t is cle a r e d in th e cc r e gis t er . o t h e r - wise, t he int e rr up t r e m a ins pe nd ing u n t il bo th co ndit i on s be co me t r u e . cle a ri ng th e in put ca pt ure in te rr upt re que st ( i . e . c l ea r i ng th e ic f i b i t) is do ne in t w o st ep s: 1. rea d ing t he sr r egist er wh ile t h e icf i bit is se t. 2 . an ac ce ss (r ea d or w r ite ) to th e ic i lr r egist er . not e s : 1 . afte r r e a d i ng th e ic i hr re giste r , t r a n sf er of in put ca pt ur e dat a is inh i bit e d a nd icf i will ne ve r b e se t un til th e ic i lr r egist er is a l so re ad . 2. t he i c i r reg i ste r co nt ain s th e f r ee r u n n ing cou n t e r valu e which co rr espo nds t o t he most re ce nt in pu t cap t u r e. 3. t he 2 inpu t cap t u r e fu nctio n s can b e used to ge th er e ve n if th e tim e r a l so us es th e 2 o u t p u t com par e f unct i ons. 4. i n one p u lse m ode an d pwm mod e o n ly i n p u t ca pt ur e 2 ca n b e u se d . 5. t he alt e r nat e inpu ts (i cap1 & i c ap2 ) a r e alw a y s d i re ctly co nn e cte d to th e t i me r. so an y t r ansit ions o n th ese p i ns a c t i vat e s t h e inp u t ca pt ur e fu nc tion . m o re over if one of t h e i c ap i pi ns is co nf igur ed a s an inp u t an d t h e secon d o ne as an o u t put , a n in te rr up t ca n b e gen era t ed if th e u ser to g- gle s th e o u t p u t p i n an d if t h e i c ie bit is se t. t h is can be a v o i ded if t he in put capt ur e f unc- tio n i is disab l ed b y r ead ing t h e ic i hr (s ee note 1) . 6. t he t o f b i t ca n be used with int e r r u p t ge ner a- t i on in or der t o mea s u r e event s th at go b e yond t h e t i me r ra nge (fff fh) . 7. i n f l ash de vices, th e i c ap2 r e g i st er s (t aic 2 h r , t a ic 2l r) ar e n o t av aila b l e o n t i mer a. the co rr espo ndin g in te rr upt s cann ot b e used ( i cf2 is fo rced b y ha rd wa re t o 0) . ms byte ls byte ici r ic i hr ic i lr 1 st72324jx st72324kx 64/164 16- bit timer ( c ont ?d) figure 3 9 . inpu t ca ptu r e blo ck dia g ram figure 40. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control regis t er 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 ic ap1 ic ap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 tim e r clo c k co unter register icapi pin i c ap i f l ag ic api register note: the rising edge is the a ctive edge. 1 st72324jx st72324kx 65/164 16- bit timer ( c ont ?d) 10. 3. 3. 4 o u tpu t compare in t h is sectio n, t he in de x, i , ma y b e 1 or 2 becau se th er e ar e 2 out pu t co mpar e f u n c t i o n s in t he 1 6 - b it tim e r. t h is fu nc tion ca n be use d t o co nt ro l a n o u t p u t wa ve fo rm or in dicat e wh en a per iod o f tim e h a s elap se d. wh en a m a t c h is f o u nd bet ween t h e ou tp ut com- par e re giste r an d th e fr ee r unn ing cou n t e r , t he ou t- p u t c o m p ar e fu nc tio n : ? a ssign s p i ns with a pr og rammable value if the oc i e bit is set ? s et s a f l ag in t h e st at us r e g i st er ? g en er at es an int e r r u p t if en able d two 16 -bit r egist er s o u t put comp are regist er 1 (o c1 r) an d o u t put comp ar e reg i st er 2 (o c2 r) co nt ain th e valu e t o b e com par ed to t he co unt er re gi s t e r ea ch t i me r cl o c k c y c l e. the s e reg i ste r s ar e re ada ble and wr ita b le and are n o t af fec te d b y the tim e r ha rd wa re . a re se t ev en t ch ang es th e oc i r va lue t o 80 00h . timing r e solu tio n is on e co unt o f t he f r e e r u n n ing co unt er : ( f cpu/ cc[1: 0] ). pr oce dure : t o us e th e ou tp ut co mp a r e fu nc tion , s e le ct t h e fo l- lowing in the cr2 register: ? se t t he oc i e bit if a n o u t p u t is nee de d t h e n t h e ocmp i pin is d edicat e d to th e ou t put comp are i sig nal. ? se lec t t h e t i me r clo ck (cc [ 1 : 0 ] ) (se e ta ble 16 cl o c k co nt ro l b i t s ). a n d select the following in the cr1 register: ? se le ct th e ol vl i bit to a p p lied t o th e ocmp i pin s af te r t he ma tch occur s . ? set t h e o c i e bit t o ge ner at e an int e r r upt if it is nee ded . wh en a ma tch is fo und be twee n o c ri r e g i st er and cr r e g i st er : ? o c f i b i t is se t. ? t h e o c m p i p i n ta ke s o l vl i bit va lue ( o cmp i p i n lat ch is f o r c e d low dur ing r e set ) . ? a t i me r int e r r u p t is gen er at ed if th e ocie bit is se t in th e cr1 reg i ste r an d t he i bit is cle a r ed in t h e cc re giste r (cc). the oc i r r e g i st er valu e r equ ire d f o r a sp ecific t i m- ing a pplicat ion can b e calculat e d using th e f o llow- ing f o r m ula: wh ere : ? t = ou tp ut com par e pe rio d (in secon d s) f cpu = cpu clock f r e que ncy ( i n her t z ) presc = time r pr escaler f a ct or ( 2 , 4 or 8 d e - pe ndin g o n cc[ 1 :0 ] b i ts, see table 16 clock control bits ) i f th e tim e r clo ck is a n ex te rn al clo ck , th e fo rm u l a is : wh ere : ? t = ou tp ut com par e pe rio d (in secon d s) f ext = ex te rn al t i me r c l oc k fr eq u e n cy ( i n h e r t z) cle a ri ng th e ou tp ut comp are inte r r u p t re qu est ( i . e . c l ea r i ng th e o c f i bit ) is don e by: 1. rea d ing t h e sr r egist er while t he ocf i bit is set. 2. an a c ce ss (r ea d or wr ite ) t o t h e o c i lr reg i st er . the fo llowing pro cedu re is r e com m en ded to pr e- v e n t th e oc f i b i t fr om b e ing set bet ween t h e t i me it is re ad a n d th e writ e to th e oc i r re gis t e r : ? writ e to t h e oc i h r r e g i st er ( f ur th e r c o m p ar es ar e inh i bit e d ) . ? re ad th e sr r e g i st er (fir st s t e p o f th e c l ea ra n ce of th e oc f i bit , w h ic h may be already set). ? writ e to t h e oc i l r re gis t e r ( e na ble s th e ou tp ut co mpar e f unct i on a nd clear s t h e o c f i bit ) . ms byte ls byte oc i ro c i hr o c i lr ? oc i r = ? t * f cpu presc ? oc i r = ? t * f ext 1 st72324jx st72324kx 66/164 16- bit timer ( c ont ?d) no tes : 1. af t e r a p r o c e s sor writ e cycle t o th e o c i hr r eg- ist e r , th e out pu t comp are f u n c t i on is in hibit e d u n t il th e oc i lr r e g i st er is also writ t en. 2 . if th e o c i e b i t is not set , t he ocmp i pin is a g e n e ra l i / o por t and t he o l vl i bit w ill not a p p ear when a ma tch is f o u n d but an int e r r u p t cou l d be g ene ra te d if t h e o c i e bit is se t. 3. wh en t h e t i mer clo c k is f cpu /2, oc f i and ocm p i a r e set while t h e cou n t e r valu e equ als th e o c i r r egist er va lue ( s e e figu re 4 2 on p age 67 ) . this b eha vio u r is t he sa me in o p m or pwm mod e . wh en t he t i mer clo c k is f cpu /4 , f cpu /8 o r in e x t e rna l clock mode , ocf i an d o c m p i ar e set wh ile th e co un te r va lue eq ua ls th e o c i r regis - t e r va lue p l us 1 ( s ee figu re 4 3 on p age 6 7 ). 4. t he o u t put compa r e fu nctio n s ca n be u s e d bo th f o r ge ner at ing e x te rna l event s on t h e ocmp i p i ns even if t he in pu t ca pt ure mo de is a l so us ed . 5. t he valu e in t h e 1 6 - b it oc i r r egist er a n d t h e ol v i b i t sh ould be ch ang ed af te r each su c- cessf ul comp ar iso n in ord e r t o cont r o l an ou tp ut wave fo rm or esta blish a ne w ela p sed t i meo u t . 6. i n f l ash de vice s, t he t a oc2hr, tao c 2 l r re gis te r s ar e ? w r i te on ly? in t i m e r a. t h e c o r r e - spo ndin g e v e n t ca nno t b e ge ne rat e d (o cf 2 is f o r c ed by har dwar e t o 0) . forc e d c o mpa r e out p ut c a pa bilit y wh en th e fol v i bit is se t by sof t w a r e , t he olvl i bit is cop i ed t o th e ocmp i pin . t h e o l v i bit ha s t o be t ogg led in or der to t o g g le t he ocmp i pin when it is ena bled (o c i e bit = 1) . th e ocf i b i t is th en n o t s e t by ha r d w a r e , an d th us no in te rr up t r e q u e s t is gen er at ed. the fo lvl i bit s ha ve no e f f e ct in bo th o ne pu lse mode and pwm mod e . figure 4 1 . outp ut compare block diagr a m output compare 16-bit cir cuit oc 1 r register 16 bit free running counter oc 1e cc0 cc 1 oc2 e olvl1 ol vl 2 oc ie (control register 1) cr1 (control register 2) cr 2 0 0 0 ocf2 oc f1 (status register) sr 16-bit 16-bit ocmp 1 ocmp 2 la tch 1 la tc h 2 oc2r register pi n pi n fol v 2 fo l v 1 1 st72324jx st72324kx 67/164 16- bit timer ( c ont ?d) figure 4 2 . outp ut compare t i ming dia g ra m , f timer =f cpu /2 figure 43. output compare timing diagram, f timer =f cpu /4 in ternal cpu c l ock timer cloc k counte r reg i ste r ou t p ut co mpare reg i ster i (o cr i ) o u tput c o mpar e flag i (o cf i ) ocm p i pin (o lvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf in ternal cpu c l ock tim er c l ock co unter register output comp are register i (ocr i ) co mpare reg i ster i latch 2ed3 2ed0 2ed 1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output com pare flag i (ocf i ) 1 st72324jx st72324kx 68/164 16- bit timer ( c ont ?d) 10. 3. 3. 5 o n e pul se mod e one pu lse mod e ena bles t he ge ne rat i on of a pulse whe n an ext e r nal e v e n t o c cur s . th is mo de is se lecte d via th e opm bit in th e cr2 r egist er . the one pulse mod e uses t h e in put cap t u r e1 fu nctio n an d th e out p u t comp ar e1 f u n c t i on . pr oce dure : to use on e pulse mo de : 1 . lo ad th e oc 1r re gis t e r wit h t h e va lu e co r r e - spo n d i ng t o t he le ngt h of t he p u lse (see th e fo r- mu la in th e op p o s i te co lum n ). 2. select the follow i ng in the cr 1 regis t er: ? u sin g th e ol vl1 b i t, select t h e level t o be ap- plie d to t h e o c m p 1 pin af t e r t h e p u lse. ? u sin g th e ol vl2 b i t, select t h e level t o be ap- plie d to t h e o c m p 1 pin du rin g th e pulse . ? s elect t h e ed ge of th e a c t i ve tr an sit i on o n t h e icap1 pin wit h th e i e dg1 bit (t he icap 1 p i n m u st be c o n fig ur ed a s flo a t i ng in pu t) . 3. select the follow i ng in the cr 2 regis t er: ? s et th e oc1e bit , th e ocmp1 p i n is th en d ed- ica t ed t o th e out p ut com par e 1 f unct i on. ? s e t th e opm b i t. ? s elect t h e t i mer clock cc[1 : 0 ] (see t able 16 clo c k cont r o l bit s ). the n , on a vali d eve n t on th e i c ap1 p i n, t he co un- ter is initializ ed to fffc h a n d ol vl2 bit is loa ded o n th e o c m p 1 pin , th e icf1 b i t is se t an d th e va l- ue fff dh is loa ded in t h e i c 1r reg i ste r . be cause th e i c f1 bit is set whe n a n a c t i ve e dge occu rs, an in te rr upt ca n b e gen er at ed if t he i c i e b i t is s e t . cle a ri ng th e in put ca pt ure in te rr upt re que st ( i . e . c l ea r i ng th e ic f i b i t) is do ne in t w o st ep s: 1. rea d ing t he sr r egist er wh ile t h e icf i bit is se t. 2 . an ac ce ss (r ea d or w r ite ) to th e ic i lr r egist er . the o c 1 r r egist er va lue r equ ire d fo r a spe c if ic timin g a pplicat ion ca n b e calculat e d using th e f o l- lowing f o r m ula : wh ere : t = pulse pe rio d (in secon d s) f cpu = cpu clock f r e que ncy ( i n her t z ) presc = time r p r e s cale r f a ct or (2, 4 or 8 de pen d- in g o n th e cc [1 :0 ] b i ts , se e ta ble 16 clock control bits ) if th e t i mer clo c k is an e x t e r nal clock th e f o rm ula is: wh ere : t = pulse pe riod (in secon d s) f ext = ex te rn al t i me r c l oc k fr eq u e n cy ( i n h e r t z) wh en t h e value of t he co unt er is equ al t o t h e value o f th e co nt en ts o f t h e o c 1 r r e gis ter , th e ol vl 1 bit is out pu t o n th e ocmp1 pin , (se e figu re 4 4 ). not e s : 1. t he ocf1 bit can n o t be se t b y ha rd wa re in one p u lse mod e bu t t h e o c f 2 bit ca n ge ner at e an o u t put compa r e in te rr up t. 2. whe n t he pulse widt h mo dula t io n ( p wm) and on e puls e m o de ( o pm ) bit s a r e bo th se t, th e pwm m o de is th e on ly ac tive o n e . 3. if olvl1=olvl2 a co ntinuous s i gnal will be se en o n th e oc mp 1 pin . 4. t he i c ap1 pin can n o t be u s e d t o pe rf or m inp u t cap t u r e . th e icap2 pin can b e used t o per f o rm in put capt ur e ( i cf2 ca n be se t a nd i c 2r ca n be lo ade d) but t h e user must t a ke car e t h a t t h e cou n t e r is r e set each t i me a va lid ed ge o c cur s o n t he i c ap1 pin a nd i c f1 can a l so gen er at es in te rr up t if i c ie is se t . 5. whe n on e pu lse mod e is used o c 1 r is de di- ca te d to th is m o de . ne ve rth e l es s o c 2 r a n d o c f 2 can b e used to in dicat e a p e r i od of t i me h a s b e e n elap se d but cann ot g ene ra te a n out - p u t wavef o r m becau se t h e le ve l ol vl2 is de di- cat e d t o t h e o ne pu lse mode . 6 . in flas h de vice s, tim e r a ocf2 b i t is fo rc ed b y ha rd wa re t o 0. event occurs counter = oc 1r oc mp 1 = o l v l 1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 co unt er is re set to fffch icf1 b i t is se t i c r1 = co unt er oc i r v a l u e = t * f cpu presc - 5 oc i r = t * f ext -5 1 st72324jx st72324kx 69/164 16- bit timer ( c ont ?d) figure 4 4 . one pulse mod e tim i ng exa m ple figure 45. pulse width modulation mode timi ng example with 2 output compare functions coun t e r fffc fffd fffe 2ed 0 2ed1 2e d2 2ed3 fffc fffd ol vl2 ol vl2 olvl1 ic ap1 ocm p 1 comp ar e1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 01f8 01f8 2ed3 ic1r counte r 34e2 34e2 fffc ol v l 2 ol vl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 fffc fffd fffe 2ed0 2ed1 2ed2 1 st72324jx st72324kx 70/164 16- bit timer ( c ont ?d) 10.3.3.6 pulse width m odulat io n m ode pu lse widt h mo du lat i on ( p wm) m ode ena ble s t h e gen er at ion of a signa l wit h a f r e que ncy a nd pu lse leng th det er min ed b y t h e va lue o f t h e oc1r and oc2r r e g i st er s. pu lse wid t h mod u lat i on mode uses th e co mple te out p u t co mpar e 1 fu nct i on p l us th e o c 2 r r e g i s- te r, and so t h is fu ncti ona lity ca n no t be u s ed when p w m m o d e is act i va te d. in pwm mo de , d o u b l e buf f e r i ng is imple m en te d on th e ou tp ut co mpa r e r e g i st er s. any new value s wr it- te n in t he o c 1 r a nd o c 2 r r egist er s a r e t a ken int o accou n t only at t he e n d of th e pwm pe riod (o c2 ) t o avoid sp ikes on t h e pwm o u t put pin (o cmp1 ). pr oce dure to use pu lse wid th mo du lat i on mo de: 1 . lo ad th e oc 2r re gis t e r wit h t h e va lu e co r r e - spo n d i ng t o th e pe riod of t h e sign al using t h e f o r m u l a in th e opp osit e co lumn . 2 . lo ad th e oc 1r re gis t e r wit h t h e va lu e co r r e - spo n d i ng to t he per iod of t h e pu lse if (o lvl1 =0 an d ol vl 2= 1) u s in g th e fo rm ula in t h e o p p o - site column. 3. select the follow i ng in the cr 1 regis t er: ? u sin g th e ol vl1 b i t, select t h e level t o be ap- plie d to t h e o c mp1 pin a f t e r a su ccessfu l co mpa r ison wit h th e oc1r re giste r . ? u sin g th e ol vl2 b i t, select t h e level t o be ap- plie d to t h e o c mp1 pin a f t e r a su ccessfu l co mpa r ison wit h th e oc2r re giste r . 4. select the follow i ng in the cr 2 regis t er: ? s et oc1e b i t: t h e ocmp1 pin is t h en d e d i ca t- ed t o t he ou tp ut co mpar e 1 f unct i on . ? s et t h e pwm bit . ? s elect t he tim e r clock (cc[1 : 0 ] ) ( s e e t able 16 clo c k cont r o l bit s ). if ol vl 1=1 a nd o l vl2 = 0 th e le ngt h o f t h e posi- tive pulse is th e d i ff er en ce be twee n t h e o c 2 r and oc1r r e g i st er s. if olvl1=olvl2 a c o nti nuous s i gnal will be seen on t he ocmp1 p i n. the oc i r r e g i st er valu e r equ ire d f o r a sp ecific t i m- ing a pplicat ion can b e calculat e d using th e f o llow- ing f o r m ula: wh ere : t = sign al or p u lse per iod ( i n second s) f cpu = cpu clock f r e que ncy ( i n her t z ) presc = time r p r e s cale r f a ct or (2, 4 or 8 de pen d- in g on c c [1 :0 ] b i ts , s e e tab l e 16 ) if th e t i mer clo c k is an e x t e r nal clock th e f o rm ula is: wh ere : t = signa l or pu lse per iod ( i n second s) f ext = ex te rn al t i me r c l oc k fr eq u e n cy ( i n h e r t z ) the ou tp ut comp ar e 2 eve n t causes th e cou n t e r to be initialized to fffc h (see fig u r e 45 ) not e s : 1. af t e r a writ e instr u ct ion t o th e o c i hr reg i st er , t h e out pu t comp ar e f unct i on is inhib i t ed un til t h e oc i l r r egist er is also writ te n. 2. t he o c f 1 a nd o c f 2 bit s cann ot be se t by h a r d war e in pwm mode t h e r e f o r e t he ou tp ut com par e int e r r u p t is inh i bit ed. 3. t he i c f 1 bit is set by h a r d war e wh en t h e cou n - t e r rea c h e s th e oc2r valu e an d ca n pr odu ce a tim e r in te rr up t if the icie b i t is se t an d th e i bit is clea re d. 4. i n pwm mod e th e i c ap1 p i n can no t be used t o pe rf or m inpu t cap t u r e be cause it is disco n - n e cte d t o t he t i mer . t he i c ap2 pin can b e used t o pe rf or m inpu t capt ur e (i cf2 can be set and i c 2r can b e lo ade d) but t he user must ta ke car e th at t he co unt er is r e set e a ch p e r i od and icf1 ca n a l so ge n e r a tes in te rr up t if ic ie is se t. 5. whe n t he pulse widt h mo dula t io n ( p wm) and on e puls e m o de ( o pm ) bit s a r e bo th se t, th e pwm m o de is th e on ly ac tive o n e . 6. i n f l ash de vice s, t he t a oc2hr, tao c 2 l r re gis t e r s in t i me r a a r e ?w rite on ly? . a re a d o per at ion r e t u r n s an un def ine d value . 7. i n flash de vices, t h e i c ap2 r e g i st er s (tai c2hr, tai c 2lr) ar e no t availab l e in timer a. the icf2 bit is forced by hardware to 0. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl 1 when when = oc1r pulse width modulation cycle coun te r is r e set to ff fch icf1 b i t is s e t oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 1 st72324jx st72324kx 71/164 16- bit timer ( c ont ?d) 10. 3. 4 lo w po wer mo des 10. 3. 5 i n t e rrup t s no te: the 1 6 -b it tim e r in te rr upt event s a r e con n e c t e d t o t he same in te rr up t vecto r (see in te rr upt s cha p - t e r ) . t h es e e v e n t s ge ne r a t e an int e r r u p t if th e co rr es po n d in g en a b le co ntr o l bit is s e t a n d th e in te rr up t mask in the cc regis t er is reset (ri m ins t ruct ion). * in f l ash devices, t h e i c f2 a nd ocf2 b i ts ar e f o rced by h a r d war e to 0 in timer a, he nce t her e is n o in- te rr upt even t f o r t h e s e f l ag s. 10. 3. 6 summar y of ti mer mode s 1 ) se e no te 4 in sect ion 10 .3 .3 . 5 one pu lse m ode 2) see n o t e 5 an d 6 in sectio n 10 .3 .3 .5 o ne pulse mo de 3 ) se e no te 4 in sect ion 10 .3 .3 . 6 pu lse wid t h m odu lat i on mo de 4) in fla s h de vice s, t h e taoc2hr, taoc2l r re gist e r s a r e wr it e o n ly in timer a. ou tp ut comp ar e 2 event cann ot b e gen er at ed, ocf2 is fo rced b y ha rd wa re t o 0. 5) in flash devices, input capture 2 is not implemented in timer a. icf2 bit is forced by hardware to 0. mode description wa i t no e f fect on 16-bit timer. tim e r interrupts cause the device to exit from wa it mode. ha l t 16-bit timer regist ers are frozen. in halt mode, the c ounter stops counting until halt m ode is ex ited. counting re sumes from the previous count when the mc u is w o k en up by an interrupt with ?e x i t from halt mode? ca pabi lity or from the counter reset value when the mc u is woken up by a re set. if an in put c apture event occ u rs on th e icap i pin, the input capture detecti on circ uitry is arm ed. consequent- ly, when the mcu is woken up by an interrupt wi th ?ex i t from halt mode? capability, the icf i bit is set, and the counter value p r esent when exiting fr om ha lt mode is captured into the ic i r register. interrupt event event flag enable control bit exit fr om wa i t exit from halt input capture 1 ev ent/c o unter reset in pwm m ode icf1 ici e ye s n o input capture 2 ev ent icf2 * ye s n o o u tput compare 1 event (not available in pwm m o de) o c f1 ocie ye s n o o u tput compare 2 event (not available in pwm m o de) ocf2 * ye s n o timer overflow event tof t oie y es no mo d e s timer resou rces input c ap t ure 1 i nput captur e 2 o utput compare 1 o utput compare 2 input capture (1 and/or 2 ) yes y es 2) 5 ) yes y es 4) o u tput compare (1 and/or 2) yes y es 5) yes y es 4) o ne puls e mode no not rec om m ended 1)5) no partially 2) p w m mode no not rec om m ended 3)5) no no 1 st72324jx st72324kx 72/164 16- bit timer ( c ont ?d) 10. 3. 7 regi st er des c ri pt ion ea ch t i mer is a s sociat ed wit h th ree con t r o l and st at us re giste r s, a nd wit h six pair s o f da t a reg i ste r s (1 6-b i t value s ) r e la tin g t o t he two inp u t capt u r es, th e t w o ou tp ut comp are s , t h e co un te r a nd t h e al- te rn at e co unt er . co nt ro l re g i s t e r 1 (c r1 ) re ad/ writ e re se t valu e: 0 0 0 0 000 0 (0 0h) bi t 7 = ici e i npu t capt u r e i n t e r r u p t en able . 0 : in te rr up t is in hib i te d . 1 : a tim e r inte r r u p t is ge ne r a t e d wh en ev er th e icf1 o r icf2 b i t o f t h e s r r e g i st er is se t. bi t 6 = oc ie out p u t comp ar e in te rr up t enab le. 0 : in te rr up t is in hib i te d . 1 : a tim e r inte r r u p t is ge ne r a t e d wh en ev er th e oc f1 o r o c f2 bit of th e sr re g i s t e r is se t. bi t 5 = toie tim e r ove r f l ow i n te rr upt enab le. 0 : in te rr up t is in hib i te d . 1: a t i me r int e r r u p t is ena bled when ever th e to f b i t of th e sr r egist er is se t. bi t 4 = folv2 for c ed ou tp ut co mpa r e 2 . this b i t is se t an d cle a r ed b y sof t war e . 0: no ef f e ct o n th e ocmp2 pin . 1: fo rces th e ol vl2 b i t t o be co pied t o t h e o c mp2 pin, if th e oc2e bit is se t a nd e v e n if th er e is no su cc es sful comparison. bi t 3 = folv1 for c ed ou tp ut co mpa r e 1 . this b i t is se t an d cle a r ed b y sof t war e . 0: no ef f e ct o n th e ocmp1 pin . 1: fo rces ol vl1 t o b e copie d t o t he o c m p 1 pin, if th e oc 1e bit is se t an d ev en if th er e is n o su c- cessf ul comparison. bi t 2 = olvl2 ou tp ut l e v e l 2. this bit is copie d t o t h e ocmp2 pin wh ene ve r a su ccessfu l com par ison occur s with t h e o c 2 r re g- is ter and oc xe is set in the cr2 register. this val- ue is co pied t o t h e ocmp1 pin in o n e pulse m ode and pu lse widt h mo dula t io n mod e . bi t 1 = ied g 1 i npu t edg e 1. this bit determines which t y p e of le vel tr an sit i on on the ic ap1 pin w ill trigger the c a pture. 0: a falling edge tr iggers the c a pture. 1: a rising e d g e tr igg e rs th e capt ur e. bi t 0 = olvl1 ou tp ut l e v e l 1. the ol vl1 bit is co pie d t o t he ocmp1 pin whe n - ever a succe s sf ul co mpa r ison o c cur s with t h e oc1r register and the oc1e bit is set in the cr2 register. 70 icie o c ie toie f o lv2 f olv1 olvl2 i edg1 o l vl1 1 st72324jx st72324kx 73/164 16- bit timer ( c ont ?d) co nt ro l re g i s t e r 2 (c r2 ) re ad/ writ e re se t valu e: 0 0 0 0 000 0 (0 0h) bi t 7 = oc 1e ou tp u t co m p ar e 1 pin ena b l e. this b i t is used o n ly t o out pu t t he signa l f r o m t h e tim e r on t he ocmp1 pin ( o lv1 in out p ut com- par e mod e , b o t h olv1 a nd ol v2 in pwm and o n e - p u l se m o de ). wh at ev er th e v a lu e of th e oc1 e bit , t he ou tp ut co mpa r e 1 f unct i on o f t he t i mer r e - mai n s ac t i ve . 0: ocmp1 p i n alt e r n a t e fu nctio n d i sa bled (i / o pin f r e e f o r ge ne ral- pu rp ose i/ o) . 1: o c m p 1 pin alt e r n a t e f u n c t i o n ena bled . bi t 6 = oc 2e ou tp u t co m p ar e 2 pin ena b l e. this b i t is used o n ly t o out pu t t he signa l f r o m t h e tim e r on t he ocmp2 pin ( o lv2 in out p ut com- par e mod e ) . what ever t h e valu e of t h e o c 2 e bit , th e ou t put comp ar e 2 f un c t i o n of t he time r r e- mai n s ac t i ve . 0: ocmp2 p i n alt e r n a t e fu nctio n d i sa bled (i / o pin f r e e f o r ge ne ral- pu rp ose i/ o) . 1: o c m p 2 pin alt e r n a t e f u n c t i o n ena bled . no te: in f l as h d e v i ces , th is b i t is no t av aila b l e fo r timer a. i t must be kept at it s reset va lue . bi t 5 = opm on e pu lse m o d e . 0: o ne pulse mo de is n o t active. 1: o ne pu lse m ode is a c t i ve, th e i c ap1 p i n ca n be u s e d to tr igge r on e pu lse o n t he ocmp1 p i n; t h e a c t i ve t r an sitio n is g i ven by t he i e dg1 b i t. the le ngt h o f th e ge ner at ed pu lse dep end s on t h e con t e n t s of t he oc1r re giste r . bi t 4 = pwm pulse wid t h m odu lat i on . 0 : pwm m o de is n o t ac tive . 1 : pwm m o d e is ac tive , th e oc mp 1 pin ou tp ut s a p r og ra mmab l e cyclic sig nal ; t he le ngt h o f t h e p u lse de pen ds on t h e va lue o f o c 1 r reg i st er ; t h e per iod d e p end s o n t he valu e of oc2 r r egis- te r. bit 3, 2 = cc [1 :0 ] clock control. the t i mer clo c k mod e dep en ds o n th ese bit s: tabl e 16 . clo ck cont rol bi ts not e : if th e ext e rn al clock pi n is no t availa ble , pr o- g r am m i ng th e ex te rn al cloc k co n fig ur at ion st op s th e co unt er . bi t 1 = ied g 2 i npu t edg e 2. this bit determines which t y p e of le vel tr an sit i on on the ic ap2 pin w ill trigger the c a pture. 0: a falling edge tr iggers the c a pture. 1: a rising e d g e tr igg e rs th e capt ur e. bi t 0 = exedg e xternal clock edge. this bit determines which t y p e of le vel tr an sit i on on the external clock pin ex tc lk will trigger the co unt er reg i ste r . 0: a falling edge triggers the c o unter register. 1: a rising e d g e tr igg e rs th e coun te r re gist er. 70 oc1e o c 2e o p m p w m c c 1 cc0 iedg2 e xedg timer clock cc1 cc0 f cpu / 4 0 0 f cp u / 2 0 1 f cp u / 8 1 0 extern al clock (where available) 11 1 st72324jx st72324kx 74/164 16- bit timer ( c ont ?d) co nt ro l/ st at us r e g i s t e r (c s r ) re ad on ly ( e xce p t bit 2 r/ w) r e s e t value: xxxx x0xx (x xh) bi t 7 = icf1 i npu t capt u r e fla g 1. 0: no inp u t ca pt ur e (r eset valu e) . 1: an inp u t capt ur e has o c cur r e d on th e i c ap1 pin o r th e co unt e r has re ached t h e o c 2 r value in pwm mo de. to cle a r th is bit , f i r s t r ead th e sr r egist er , t h e n r ead or wr it e t he lo w b y t e o f t h e i c 1r ( i c1 lr) re gist er. bi t 6 = oc f1 out p u t comp ar e flag 1 . 0: no ma tch ( r ese t value ) . 1: t he co nt ent of t he fr ee ru nn ing co unt er h a s ma tch ed t he cont en t of th e oc1r r e g i st er . to clea r t h is b i t, fir s t r ead t h e sr re giste r , th en r ead o r wr ite t h e low byte o f th e o c 1r ( o c1lr) r eg- ister. bi t 5 = tof time r over flo w fla g . 0: no t i mer over flo w (r eset va lue ) . 1: th e fre e ru nnin g co un te r ro lled o v e r fro m ffffh t o 00 00h . to clear t h is bit , f i rst re ad t he sr r eg- ist e r , th en re ad or wr ite t he low b y te of th e cr ( c l r ) re giste r . no te: re adin g or writ in g th e acl r re giste r do es not cle a r t o f. bi t 4 = icf2 i npu t capt ur e fla g 2. 0: no inp u t ca pt ure ( r e set valu e) . 1: an inp u t ca pt ure h a s o c cu rr ed on t h e i c ap2 p i n. to clea r t h is b i t, f i rst re ad t h e sr reg i st er , t h e n r ead or writ e th e lo w byt e o f th e i c 2r (i c2 lr ) r e g i st er . n o te : i n flash de vices, t h is bit is n o t ava ilable f o r timer a an d is f o r c e d by har dwar e t o 0. bi t 3 = oc f2 out p u t comp ar e flag 2 . 0: no ma tch ( r eset value ) . 1: th e co nt ent o f th e fr ee ru nnin g co unt er h a s ma tche d th e co nt en t of th e oc2r r e g i st er . to clea r th is b i t, fir s t r ead t h e sr re giste r , th en r ead o r wr ite t h e low byte of th e o c 2 r (o c2lr) re g- ister. n o te : i n flash de vices, t h is bit is n o t ava ilable f o r timer a an d is f o r c e d by har dwar e t o 0. bi t 2 = timd timer disable . this bit is set a nd clea re d by sof t war e . when se t, it f r e e z es th e t i me r pr es ca ler an d co un te r a n d d i sa - bled t h e o u t put f unct i ons (o cm p1 a n d o c mp2 pins) t o r e d u ce po we r con s umption. access to the timer registers is still av a ilabl e, allowing the timer co nf igur at ion t o be ch ang ed, or t he co unt er r eset , w h ile it is dis a bled. 0: tim e r e nab led 1: tim e r p r escale r, co unt er and o u t put s d i sable d b i ts 1:0 = re se rv ed , mu st be kept cleared. 70 icf1 oc f1 tof i cf2 o cf2 t imd 0 0 1 st72324jx st72324kx 75/164 16- bit timer ( c ont ?d) input captur e 1 high register (ic1hr) re ad on ly r e s e t value: undefined t h is is a n 8- bit r e a d on ly re gis t e r th at co nt ain s th e high p a r t o f t he cou n t e r valu e (t r ansf e r r ed by t h e in p u t ca pt ur e 1 ev en t) . input captur e 1 low re gis te r (ic1lr) re ad on ly r e s e t value: undefined t h is is a n 8- bit r e a d on ly re gis t e r th at co nt ain s th e lo w p a r t of th e co un te r valu e (t ra ns fe rr ed b y t h e in - put ca pt ur e 1 even t) . outpu t c o mpar e 1 high register (oc1hr) re ad/ writ e r e s e t va lue : 10 0 0 00 00 ( 8 0h ) this is an 8- bit r e g i st er t h a t cont a i ns t h e hig h par t of t h e valu e t o be comp are d t o th e chr r e g i st er . outpu t c o mpar e 1 low register (oc1l r ) re ad/ writ e r e s e t va lue : 00 0 0 00 00 ( 0 0h ) this is a n 8- bit re giste r t h a t con t a i ns th e low pa rt of th e va lue t o be comp ar ed t o t he clr r e g i st er . 70 msb l sb 70 msb l sb 70 msb l sb 70 msb l sb 1 st72324jx st72324kx 76/164 16- bit timer ( c ont ?d) outpu t compar e 2 high r egister (o c2 hr ) re ad/ writ e re se t valu e: 1 0 0 0 000 0 (8 0h) this is an 8- bit r e g i st er th at con t a i ns t h e h i gh pa rt of t h e va lue t o be comp ar ed t o th e chr reg i ste r . no te: i n flash devices, th e t i mer a o c 2 h r r e g i s- ter is write-only . outpu t compar e 2 low r e gister (o c2 lr) re ad/ writ e re se t valu e: 0 0 0 0 000 0 (0 0h) this is a n 8- bit re giste r t h a t con t a i ns th e low pa rt of th e va lue t o be com par ed t o t he clr reg i st e r . no te: in flash d e vice s, t he tim e r a oc2l r r e g i s- ter is write-only . c o u n ter high r e gister (chr ) re ad on ly re se t valu e: 1 111 1 1 1 1 (ff h ) this is an 8- bit r e g i st er t h a t cont a i ns t h e hig h par t o f th e co un te r va lue . co un te r l o w r e gi s t e r ( c lr ) re ad on ly re se t valu e: 1 111 1 10 0 (fch) this is a n 8- bit re giste r t h a t con t a i ns th e low pa rt of the c o unter value. a write to th is r e g i st er re se ts th e co unt er . an access t o th is r egist er a f t e r a cce ssing t h e c s r r e gist er c l ea rs th e t of b i t. 70 msb l sb 70 msb l sb 70 msb l sb 70 msb lsb 1 st72324jx st72324kx 77/164 a l ter nate c o un ter high r e gister (ach r) re ad on ly re se t valu e: 1 1 1 1 111 1 (ff h ) this is an 8- bit r e g i st er th at con t a i ns t h e h i gh pa rt of t h e co unt er va lue. al te rn a t e co un te r low re gi s t e r (aclr ) re ad on ly re se t valu e: 1 1 1 1 110 0 (fch) this is a n 8- bit re giste r t h a t con t a i ns th e low pa rt of th e coun te r valu e. a writ e t o t h is re giste r r e set s t h e co unt er . an a c ce ss to th is r egist er a f t e r an a c cess to csr r egist er do es n o t clea r th e tof bit i n t h e c s r r e gist er . inpu t captur e 2 high register (ic2hr) re ad on ly r e s e t value: undefined this is an 8 - bit re ad on ly r egist er t h a t con t a i ns t h e high p a r t of t he cou n t e r valu e (t ra nsf e rr ed b y t h e in put ca pt ur e 2 even t) . not e : in f l ash de vices, th is r egist er is no t imp l e- ment e d fo r time r a. inpu t captur e 2 low re giste r (ic2lr) re ad on ly r e s e t value: undefined this is an 8 - bit re ad on ly r egist er t h a t con t a i ns t h e lo w pa rt of th e co un te r v a lu e (t ra ns fe rr ed b y th e in - put ca pt ur e 2 event ) . not e : in f l ash de vices, th is r egist er is no t imp l e- ment e d fo r time r a. 70 msb l sb 70 msb l sb 70 msb l sb 70 msb l sb 1 st72324jx st72324kx 78/164 16- bit timer ( c ont ?d) tabl e 17 . 1 6 -bi t ti mer regi st er ma p and rese t val u es 1 in fla s h devices, t h e s e b i ts ar e not used in tim e r a and must b e ke pt clea re d. 2 in f l as h de vic e s , t h e s e b i ts ar e f o r c ed by har dwar e t o 0 in time r a 3 in flas h dev i ces, the taoc2hr and taoc 2lr regis t ers are wri t e only , readin g them w ill return unde- f i ne d value s 4 in flash devices, the taic2hr and taic2lr registers are not present. addr ess (hex.) register label 765 43210 tim e r a: 32 tim e r b: 42 cr 1 re s e t v a lu e ici e 0 oc ie 0 toie 0 fo lv2 1 0 folv 1 0 ol v l 2 0 ie dg1 0 ol vl 1 0 tim e r a: 31 tim e r b: 41 cr 2 re s e t v a lu e oc1e 0 oc2e 1 0 opm 0 pw m 0 cc1 0 cc0 0 iedg 2 1 0 exed g 0 tim e r a: 33 tim e r b: 43 cs r re s e t v a lu e icf1 x ocf1 x tof x icf2 2 x oc f 2 2 x timd 0 - x - x tim e r a: 34 tim e r b: 44 ic1hr re s e t v a lu e ms b x xx xxxx lsb x tim e r a: 35 tim e r b: 45 ic1lr re s e t v a lu e ms b x xx xxxx lsb x tim e r a: 36 tim e r b: 46 oc 1 h r re s e t v a lu e ms b 1 00 0000 lsb 0 tim e r a: 37 tim e r b: 47 oc 1 l r re s e t v a lu e ms b 0 00 0000 lsb 0 timer a: 3e 3 tim e r b: 4e oc 2 h r re s e t v a lu e ms b 1 00 0000 lsb 0 timer a: 3f 3 tim e r b: 4f oc 2 l r re s e t v a lu e ms b 0 00 0000 lsb 0 tim e r a: 38 tim e r b: 48 ch r re s e t v a lu e ms b 1 11 1111 lsb 1 tim e r a: 39 tim e r b: 49 cl r re s e t v a lu e ms b 1 11 1110 lsb 0 tim e r a: 3a tim e r b: 4a a chr re s e t v a lu e ms b 1 11111 1 lsb 1 tim e r a: 3b tim e r b: 4b ac l r re s e t v a lu e ms b 1 11111 0 lsb 0 timer a: 3c 4 tim e r b: 4c ic2hr re s e t v a lu e ms b x xx xxxx lsb x timer a: 3d 4 tim e r b: 4d ic2lr re s e t v a lu e ms b x xx xxxx lsb x 1 st72324jx st72324kx 79/164 10.4 serial per iph e ral interfac e (spi) 10.4.1 int r oduc tion the se rial per i ph er al in te rf ace ( s pi ) a llows f u ll- dup lex, syn c h r o nou s, se rial commu nicat i on with ext e rnal dev i ces. an spi sys tem may consist of a mast er a nd on e or m o r e sla v e s h o wever t h e spi in te rf ac e ca n n o t b e a m a s te r in a m u lt i-m a s te r s yst em. 10.4. 2 ma in fe at ures full du plex synchr on ous tr an sf er s ( o n 3 lin es) sim p lex synch r on ous t r an sf e r s ( o n 2 lin es) m a st er o r s l av e op e r a t io n six mast er mo de f r e q u encies (f cpu /4 m a x.) f cpu / 2 max. slave mo de f r e que ncy ( s e e no te ) ss ma nag eme n t b y sof t war e or har dwar e pr og ra mmab l e clo c k po larit y and p hase en d of tr ansf e r in te rr up t f l ag w r it e co llis ion , m a st er m o de f a ult a n d o v e r r u n fla g s not e : i n sl ave m ode , cont inu ous tr ansmission is not p o ssib le a t maximum f r e que ncy due t o t h e s o f t wa re ov er he a d fo r cle a r in g st at us f l ag s an d t o init iat e th e ne xt tr ansmission seq uen ce . 10. 4. 3 ge ner a l des c ri pt ion figur e 46 sh ows t he se ria l pe rip her al int e r f a c e (spi) block d i ag ram . th ere are 3 r e g i st er s: ? s p i c o ntrol register (spic r ) ? s pi co nt ro l/st at us re gist er ( s pi csr) ? s p i d a ta r e g i st er ( spidr) the spi is co nne cte d t o ext e r nal d e vices th ro ugh 4 pins: ? m is o: m a s t e r i n / sla v e o u t d a t a ? m o s i: m a s t e r o u t / sla v e in d a t a ? s c k : se ria l c l oc k ou t by sp i ma st er s an d in - put by spi sla v e s fi gure 4 6 . serial peripheral interface block diagram spidr rea d buff er 8-bit shift register write read data/address bus spi sp ie s p e ms tr cph a spr0 spr1 cpo l serial clo c k gener ator mosi miso ss sck contr o l state spicr sp i c s r interrupt request mas t er control spr2 0 7 0 7 spif w col modf 0 ov r ssi ss m so d sod bi t ss 1 0 1 st72324jx st72324kx 80/164 serial peripheral interface (cont?d) ?ss : slave select: this in put sig nal acts a s a ?ch i p sele ct ? t o let th e spi ma st er commu nicat e wit h sla v e s indi- vidually and to avoid contention on the data lines. slave ss inp u t s can be dr ive n b y sta nd- ar d i/ o po rt s o n th e mast er m c u. 10. 4. 3. 1 fu nct i o n al de scri p t i on a basic exam ple of int e r c onn ectio n s be twee n a s i ngle master and a sing le slave is illus t rated in figu re 47 . the mo si pin s ar e co nne ct e d t o get he r and t h e mi so p i ns a r e con nect ed t oge t her . i n th is way dat a is t r a n sf err e d se ria lly bet ween mast er and s l av e (m os t s i gn ific an t b i t fir s t) . the com m un ica t io n is a l wa ys init ia te d by th e mas- te r. whe n t he mast er d e vice t r ansmit s d a t a to a sla v e d e vice via mosi pin, t he slave de vice r e - sp ond s b y send ing d a t a to th e mast er d e vice via th e mi so p i n. th is im p lies full duplex communica- tio n wit h bo th da ta ou t a n d dat a in synchr onized wit h th e same clock sig nal (which is p r o v id ed by th e mast er de vice via t he sck p i n) . to u s e a singl e da ta line , t h e mi so an d mo si p i ns must b e co nne cte d at each no de ( i n t h is case o n ly s i mplex c o mmunic a tion is poss ible). four poss ible data/c lock timing relat i onships may be chosen (see figure 50 ) but master and slave must be programmed with the same timing mode. figure 4 7 . single mas t e r / single sla v e applicat ion 8-bit shift register spi clock generator 8-bit shift register mi s o mosi mosi miso sck sc k slav e mas t er ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software 1 st72324jx st72324kx 81/164 s e ria l periphera l inter f a c e (cont ?d ) 10. 4. 3. 2 sl ave se le ct m a nag e ment as an alternative to using the ss pin t o cont ro l t h e sl ave sele ct signa l, t h e ap plicat ion ca n choo se to man age t he slave se lect sig nal by sof t w a r e . this is co n f ig ur ed b y th e ssm bit in the spicsr regis - te r (see f i gur e 49 ) in software management, the external ss pin is free for other application uses and the internal ss s i gnal level is driven by w r iting to the s si bit in the spi c sr r egist er . in ma st er mode : ?s s int e r n al m u st be h e l d hig h co nt inu o u s l y in sl ave m ode: ther e ar e t w o ca se s dep end ing on t he da ta /clock timing relations h ip (see fig u r e 48 ): if cpha=1 ( d a t a la tch ed on 2 nd clock e dge ): ?s s int e r n a l m u st b e he ld low du r i ng th e en tir e trans m ission. this implies that in s i ngle s l av e applications the ss pin eit h e r can be t i ed to v ss , or mad e f r e e f o r st an da rd i/ o b y mana g- ing the ss fu nctio n by so ft war e (ssm= 1 and ssi = 0 in t he in t he spi csr r e g i st er ) if cpha=0 ( d a t a la tch ed on 1 s t clo c k ed ge) : ?s s in te rn al must b e he ld low du ring byte transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. if ss is not pulled high, a write collision error will occur when the slave writes to the shift register (see section 10.4.5.3 ). figure 4 8 . gene ric ss timin g diagr a m figure 49. hardware/software slave select management mo s i / m is o master ss slave ss (if cpha=0) slave ss (if cpha=1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin 1 st72324jx st72324kx 82/164 s e ria l periphera l inter f a c e (cont ?d ) 10. 4. 3. 3 ma st er mode oper at ion i n m a ste r m o de , th e s e r i al clo c k is ou tp ut on th e sck pin. the clock fr equ en cy, p o lar i t y an d pha se a r e co nf igu r ed by s o f t wa re (r ef er to t h e de sc rip t io n of the spics r register). no te: the idle st at e of sck m u st cor r e s p ond to the polarity s e lected in the spics r register (by pulling up sc k if c pol=1 or pulling dow n sc k if cp o l = 0 ) . to o p e r at e th e spi in mast er mod e , pe rf or m t h e following s t eps in order (i f th e spi csr r e g i st er is n o t w r it ten firs t, th e spic r r e gis t er s e t t in g (m str b i t) m a y b e no t ta ke n into a cc o u n t): 1 . writ e to th e spic r r e g i st er : ? s elect th e clock fr eq uen cy b y con f ig ur ing t h e spr[ 2: 0] bit s . ? s e l e ct th e c l oc k po la rity an d c l oc k ph a se b y c o nfiguring the cpol and cpha bits. fig u re 50 sho w s th e fo ur p o ssib le conf igu r a t io ns. no te : t h e s l av e m u st ha ve th e sa m e cpo l and cpha set t i ng s as th e mast er . 2 . writ e to th e spic s r r e gist er : ? e ith e r set t he ssm bit an d set t h e ssi bit or c l ea r th e s s m bit a n d t i e th e s s p i n hig h fo r th e comple t e byte t r ansmit se que nce. 3 . writ e to th e spic r r e g i st er : ? s et the mstr and spe bits note: mstr and spe bits remain set only if ss is high ). the t r ansmit se que nce be gins when sof t w are w r ite s a by te in th e spid r r e g i st er . 10. 4. 3. 4 ma st er mode trans m it se que nce w h e n so ftw ar e wr it es to t h e spi dr re gis t e r , th e dat a byt e is loa ded in to t h e 8 - bit sh ift re giste r and th en shif te d out ser i ally to t he mo si pin most sig- n i fic a n t bit fir s t. wh en da t a tr ansf e r is comple t e : ? t h e spif b i t is s e t by h a r d w a r e ? a n int e rr up t re qu est is ge ne rat e d if th e spi e bit is set and t he in t e rr up t m a sk in t h e ccr re giste r is clea re d. c l ea rin g th e spi f b i t is pe rf or me d by th e fo llo win g so ft war e se que nce: 1. an access to the spics r regis t er while the spif bit is set 2. a re ad t o t he spidr reg i ste r . not e : while the spif bit is s e t, all writes to the spi d r re gist er ar e inhib i t ed un til th e spi c sr re g- is ter is read. 10. 4. 3. 5 sl ave m ode op era t i o n in slave m ode , th e ser i al clo c k i s receive d o n t h e sck pin f r o m th e mast er de vice . to op era t e t h e spi in sla v e mode : 1. wr ite t o th e spi csr r e g i st er t o pe rf or m t h e f o l- lo win g act i ons: ? s elect t he clo c k po lar i ty a nd clo c k p hase by co nf igur ing th e cpol and cpha bit s (see figu re 5 0 ). no te: t h e slav e mu st ha ve t h e sa m e cpo l and cpha set t i ngs as th e mast er. ? m an age the ss pin a s d e scr i be d in section 10. 4. 3. 2 and figure 48 . if cpha=1 ss must be held low c o ntinuously. if c pha=0 ss must be held low du rin g b y t e t r ansmission and pulle d up bet ween each b y t e t o le t t h e sla v e wr it e in th e sh if t re gist er. 2. wr ite to th e spicr re giste r t o clea r t h e mstr bit and set the spe bit to enable the sp i i/o fu nc tio n s. 10. 4. 3. 6 sl ave m ode tra n smi t seq u enc e w h en software writes to th e spidr r e g i st er , t h e dat a byt e is loa ded in to t h e 8- bit sh ift reg i st e r and th en sh if te d o u t ser i ally t o t he mi so p i n most sig- n i fic a n t bit fir s t. t h e tr an sm it se qu e n c e be gin s wh en t h e s l av e de - vice r e ceives t h e clo c k signa l a nd t h e m o st signif i - ca nt b i t of th e da ta o n its mosi pin. wh en da ta t r ansf e r is co mple te : ? t he spi f bit is se t by ha rdwa re ? a n int e r r u p t re que st is ge ner at ed if spi e bit is se t an d in te rr upt mask in th e ccr r egist er is cle a r ed. c l ea r i n g th e spi f bit is pe rf or m e d by th e fo llo win g so ft war e se que nce: 1. an access to the spic s r regis t er while the spif bit is set. 2. a writ e or a r e a d to t h e spi d r r egist er . not e s : while the spif bit is s e t, all writes to the spi d r re gist er ar e inhib i t ed un til th e spi c sr re g- is ter is read. the spi f b i t ca n b e clea re d du rin g a second tr ansmission; h o wever , it m u st b e clea re d be fo re th e se cond spi f bit in or de r t o pr event an overr u n co ndit i on ( see sect ion 10 .4 . 5 . 2 ). 1 st72324jx st72324kx 83/164 s e ria l periphera l inter f a c e (cont ?d ) 10. 4. 4 cl ock pha se an d cl ock pol a rit y fou r po ssibl e tim i ng r e la tio n ships ma y b e chosen by sof t war e , u s in g t h e cpol an d cpha bit s (see figu re 50 ). no te: the idle st at e of sck m u st cor r e s p ond to the polarity s e lected in the spics r register (by pulling up sc k if c pol=1 or pulling dow n sc k if cp o l = 0 ) . the comb inat ion o f th e cpo l clock p o lar i t y and cpha ( c lock ph ase) b i ts se lect s t he da ta ca pt ure clo c k edg e figur e 50 , shows a n spi tr an sf er wit h th e fo ur co mbin at ions of t he cpha a nd cpol bit s . th e di- agr am ma y b e int e r p r e t ed a s a ma ste r or sla v e timin g d i agr am whe r e th e sck p i n, th e mi so p i n, th e mo si p i n ar e d i re ct ly co nne cte d be twee n t h e maste r an d th e slave device. not e : if cpo l is cha n g ed at t he commu n icat ion byte bo und ar ies, t he spi m u st be disab l ed by r e - setting the spe bit. figure 5 0 . dat a cloc k timing diagr a m sc k m s b it b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 l s b it msbit b it 6 b it 5 b i t 4 b i t 3b i t 2b i t 1 l s b i t mi so ( f r o m ma s t e r ) mo si (f rom sl av e) ss (t o slave) capture strobe cpha =1 msbit b it 6 b it 5 bit 4 b i t 3 b it 2 b it 1 ls b it m s b i t b it 6 b it 5 bit 4 b it 3 b i t 2 b it 1 lsb i t mi s o (fr o m m a ster) mos i ss (to slav e) c apt ur e s t ro be cpha =0 no te: t hi s fi gure shou l d not be used as a repl a c em ent for param etri c i n f orm ati on . r ef e r to the elect r ical c haracteri sti cs chap t er. (f rom sl av e) (c po l = 1) sc k (cp o l = 0) sc k (cp o l = 1) sc k (cp o l = 0) 1 st72324jx st72324kx 84/164 s e ria l periphera l inter f a c e (cont ?d ) 10. 4. 5 erro r f l a g s 10. 4. 5. 1 ma st er mode faul t ( m odf) master mode fault occurs when the master device has its ss pin pulled low. wh en a ma st er mod e fa ult o c cu rs: ? t he mo df bit is se t and a n spi in te rr upt r e - que st is g ene ra te d if t he spi e bi t is set . ? t he spe bit is reset. this blocks all output fr om th e d e vice an d di sa bles t h e spi p e r i ph- er al. ? t he mstr bit is r e set , th us f o rcin g t he d e vice int o slave mod e . cle a r i ng th e modf bit is d one t h r oug h a sof t w are se que nce: 1. a re ad access t o t he spicsr r egist er while t h e mo df b i t is se t. 2. a writ e t o th e spi cr r e g i st er . no tes : to avoid a n y con f lict s in an a pplicat ion with multiple slaves, the ss p i n m u s t be pu lle d high du rin g t h e mo df bit clea rin g seq uen ce . the spe an d m s tr bit s m a y b e r e st or ed t o th eir or ig- inal sta t e dur ing o r af te r t h is cle a rin g sequ ence. ha rd wa re do es no t allo w th e user t o set t h e spe and mstr b i ts while t he modf bit is set except in th e modf bit cle a r i ng sequ en ce . 10. 4. 5. 2 o verr un co ndi ti on ( o vr) an o v err u n con d it ion occur s , wh en t h e ma st er de- vice has sen t a dat a byte an d t h e slave device h a s not clea re d t h e spi f b i t issue d fr om th e pr eviously tr ansmit t ed b y t e . w h e n a n ov er ru n oc cu rs: ? th e ovr b i t is se t a n d an in te rr up t re qu e st is ge ne r a te d if th e spie bit is set . i n t h is cas e , th e r e c e iv er bu ffe r con ta i n s th e b yt e se nt af te r t h e spif bit was last cle a re d. a re ad to t h e spid r re gis t e r re tu rn s th is b yte . all ot he r byte s ar e lost . the o v r bit is clear ed b y re ad ing t he spicsr r e gis t er . 10. 4. 5. 3 wri t e col l i s ion err o r (wcol) a write collision occ u rs w h en the software tries to w r it e to th e spid r r e gist er wh ile a d a t a tr an sf er is ta kin g p l ace wit h an ext e r nal device. when t h is hap pen s, th e tr ansf e r con t in ues unin t e r r u p t e d ; and the software write will be unsucc es sful. w r ite c o llis ions can occ u r both in master and s l av e mode . see also se ct ion 10 .4 .3 .2 slav e selec t mana ge ment . not e : a ?read collision? will never occur since the receive d da ta byt e is pla c e d in a bu ff er in wh ich acce ss is a l wa ys syn c h r o nou s wit h t he mcu ope r- at ion. the wcol bit in th e spi csr r egist er is se t if a w r ite collis ion occ u rs. no spi int e r r u p t is gen er at ed whe n t he wcol bit is se t (th e wc ol b i t is a st at us fla g on ly) . cle a ri ng t he wco l bit is don e th ro ugh a sof t w a r e se que nce (see f i gur e 51 ). fi gure 5 1 . cl ear ing t h e wco l bi t (wri te colli si on fl ag) soft wa re se que n ce clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr re ad sp idr 2n d st e p spif =0 wc ol=0 clearing s e que nce b e fo re spif = 1 (dur in g a d a t a byt e tra n sf er) 1st st ep 2n d ste p wc ol=0 read spi csr read spidr no te: writin g to t he spidr r egis- t e r ins t e a d of re ad in g it do e s no t re se t t he wco l bit result result 1 st72324jx st72324kx 85/164 s e ria l periphera l inter f a c e (cont ?d ) 10. 4. 5. 4 si ngl e mas t e r sy st ems a t y p i ca l sing le mast er syst em ma y be conf ig ure d , using a n mcu as t he m a ste r a nd f o u r m c us as s l av es (s ee figu re 5 2 ). the ma st er device se lects th e individ ual slave de- vices by using four pins of a parallel port to control the four ss pins of th e sla v e d e vices. the ss pins ar e pulle d hig h dur ing r e set sin c e t h e master device ports will be forced to be inputs at th at t i me , t hus disab ling t he slave de vices. n o te : to pr even t a b u s conf lict on th e miso line t h e ma st er a llow s o n l y o n e ac tive s l av e de vic e d u r in g a tr an sm iss i on . for mo re secur i t y , th e slave device may re sp ond to t h e mast er wit h t h e r e ceived dat a b y t e . th en t h e master will receive the previo us by te bac k from the sla v e de vice if a ll mi so a nd m o si pins a r e co n- nect ed an d t h e slave ha s no t wr it te n t o it s spidr r e gis t er . other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. figure 5 2 . single mas t e r / mult iple slave con f igura t ion miso mo si mo si mosi mo si mo si miso miso miso mi so ss ss ss ss ss sck sck sc k sck sck 5v ports slave mcu slave mcu slave mcu slave mcu ma st er mcu 1 st72324jx st72324kx 86/164 s e ria l periphera l inter f a c e (cont ?d ) 10. 4. 6 lo w po wer mo des 10. 4. 6. 1 usi ng t h e spi t o w a k e up the mcu f r om ha lt mo de in slave co nf igu r at ion , t he spi is ab le t o wakeup th e st7 de vice fr om halt mod e t h r o u gh a spi f int e r r up t. th e dat a r e ceived is subse que nt ly r ead fr om t he spidr r e g i st er wh en t he so f t war e is r un- ning ( i nt err up t ve ct o r f et c h) . if mu lt iple dat a tr an s- fers have be en p e rf o rme d bef or e sof t wa re clea rs t h e sp if b i t, th en th e o v r b i t is s e t by h a r d war e . not e : wh en w a k i ng u p fr om ha lt m o de , if th e spi rem a ins in sla ve m ode , it is reco mmen ded t o pe r- fo rm an e xtr a commu nicat i on s cycle t o br ing t h e spi f r o m ha lt m ode st a t e to nor mal st at e. i f t h e spi exits fr om slave mo de, it r e t u rn s t o no rma l st at e imme dia t e l y. ca ution: t he spi can wake u p th e st7 fr om halt mode on ly if th e slave select signa l (e xt er na l ss pin or th e ssi bit in t he spi csr r e g i st er ) is low w h e n th e st 7 en te rs ha lt m o de . s o if sla v e se le c- t i on is co nfig u r e d a s ex te rn al (s ee section 10. 4. 3. 2 ), make sure the master drives a low level on the ss p i n when t h e slave e n t e r s halt m ode . 10. 4. 7 i n te rrup t s not e : th e spi int e r r u p t event s ar e con nect e d to t h e sa m e int e r r u p t ve cto r (se e in te rr up ts ch ap te r) . they ge ner at e an in te rr up t if t h e cor r e s pon ding en abl e co ntrol bit is set and the interrupt mask in mode description wa i t no ef fec t on spi. spi inte rrupt events cause the device to ex it from wait m o de. ha l t spi registers are frozen. in h a lt mode, the spi is ina c tive. s p i oper- ation res u m e s when the m cu is woken u p by an interrupt with ?exit from halt m ode? c a - pability. the data received is subs equently read from the s p idr r egister when the soft- ware is running (interrupt vector fetching). if seve ral data are received before the wake- up event, then an overru n error is generated. this error can be detected after the fetch of the interrupt routine t hat w o k e up the device. interrupt event even t flag enable contr o l bit ex i t fr om wa i t exit fr om halt s p i end of transfer e v ent spif spie yes y es m a ster mode fault e v ent mo d f y e s n o o v errun error o vr yes no 1 st72324jx st72324kx 87/164 s e ria l periphera l inter f a c e (cont ?d ) 10. 4. 8 regi st er des c ri pt ion co nt ro l re g i s t e r (s p i c r ) re ad/ writ e r e s e t value: 0000 x xxx (0xh) bi t 7 = spie ser i al per i ph era l in te rr upt enab le. this bit is se t an d clear ed b y sof t war e . 0 : in te rr up t is in hib i te d 1: an spi in te rr up t is g ene ra te d wh en ever spif=1, modf= 1 or ovr=1 in the spicsr r egist er bi t 6 = spe se ria l pe rip her al ou tp ut en able . this bit is set an d clear ed by sof t war e . i t is a l so cleared by hardware when, in master mode, ss =0 (see se ct ion 10 .4 .5 .1 m a st er m o de fau l t (mo df ) ). th e spe b i t is cle a r e d b y re se t, so th e s p i peripheral is not initia lly co nn ec te d to th e ex - te rn al pins. 0: i / o pin s f r ee f o r gen er al pur po se i / o 1: spi i / o pin a l te rn at e fu nctio n s ena bled bi t 5 = spr2 d i v i de r en ab le . this b i t is se t an d clea re d b y sof t war e and is c l ea re d by re se t. it is us ed wit h t h e spr [1 :0 ] b i ts t o s e t the b a u d r a te . re fe r to ta ble 18 spi ma st er m o de s c k f r eq ue n c y . 0 : divid er b y 2 en ab le d 1 : divid er b y 2 disa b l ed no te: th is b i t ha s no e ffe ct in sla v e m o de . bi t 4 = ms tr ma st er m ode . this bit is set an d clear ed by sof t war e . i t is a l so cleared by hardware when, in master mode, ss =0 (see se ct ion 10 .4 .5 .1 m a st er m o de fau l t (mo df ) ). 0: sla v e m ode 1: m a ste r mod e . the f u n c t i on o f t he sck p i n cha nge s f r o m an in put t o an o u t p u t an d t he f u n c - t i on s of th e mi so and m o si p i ns a r e r e ver s e d . bi t 3 = cpol clock polarity. this b i t is se t an d clea re d b y sof t war e . t h is bit d e - te rmin es t h e id le st at e of th e se rial clock. the cpol bit a f f e ct s bot h th e ma ste r a nd sla v e mode s. 0: sck pin has a low level idle state 1: sck p i n ha s a hig h level idle st at e not e : if cpo l is cha n g ed at t he commu n icat ion byte bo und ar ies, t he spi m u st be disab l ed by r e - setting the spe bit. bi t 2 = cph a clo ck ph as e. this b i t is se t an d cle a r ed b y sof t war e . 0 : th e fir s t clo ck tr a n s i tion is th e fir s t d a t a ca p t u r e e dge . 1: th e second clock tr ansit ion is th e fir s t capt ur e e dge . n o te : the slave mu st have t h e sam e cpo l and cpha set t i ng s as th e mast er . bi t s 1 : 0 = spr [1 :0 ] se rial clock f r eq uen cy. these b i ts ar e se t an d cle a r ed by sof t war e . used w i th th e spr2 b i t, t h e y sele ct th e ba u d r a t e of th e spi ser i al clo c k sck ou t put b y th e spi in mast er mode . note: these 2 bits have no effect in slave mode. table 18. spi master mode sck frequency 70 spie spe sp r2 ms tr cpol cpha sp r1 sp r0 ser i al clock spr 2 spr1 sp r 0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /1 6 0 0 1 f cpu /3 2 1 1 0 f cpu /6 4 0 1 0 f cpu /12 8 0 1 1 1 st72324jx st72324kx 88/164 s e ria l periphera l inter f a c e (cont ?d ) co nt ro l/ st at us r e g i s t e r (s p i cs r ) re ad/ writ e ( s o m e bit s rea d on ly) re se t valu e: 0 0 0 0 000 0 (0 0h) bi t 7 = spif se ria l pe rip her al dat a tr an sf er flag ( r ead o n ly). t h is b i t is set by h a rd wa re whe n a tr an sf er h a s b e e n comp let ed. an i n t e rr up t is g ene ra te d if spie=1 in the spic r regist er . it is clea re d b y a sof t w are se que nce (a n access t o t he spi csr r e g i st er fo llowed by a writ e or a r e a d to t h e spi dr re gist er) . 0: dat a tr ansf e r is in pr og ress o r th e f l ag h a s be en clea re d. 1: dat a t r a n sfe r be twee n t he de vice a nd an e x t e r - n a l device ha s be en comp let ed. no te: while the spif bit is se t, all writes to the spi d r r egist er ar e inh i bit ed un til t he spicsr r eg- is ter is read. bi t 6 = wcol write collision stat us (read only). this bit is s e t by hardware when a write to the spi d r r e g i st er is don e d u r i ng a tr an smi t se- que nce. i t is clea re d by a sof t war e se qu ence (see figu re 51 ). 0: no write collision oc curred 1: a write collision has been detected bi t 5 = ovr s pi over ru n er ro r (rea d on ly) . this bit is se t b y ha rd wa re whe n th e byt e cu rr ent ly bein g r e ceived in t h e shif t re giste r is r e a d y t o be tr an sf er re d in to t he spi dr r e g i st er while spi f = 1 (see sec t io n 10 .4 .5 .2 ) . an int e r r u p t is gen er at ed if spi e = 1 in spic r r egist er . the o v r bit is clea red b y so ftw ar e re ad in g th e s p icsr r e g i ste r . 0: no ove r r un er ro r 1 : ov er ru n er ro r de te ct ed bi t 4 = mo df m ode f ault fla g (rea d on ly) . this bit is set by h a rd wa re when th e ss pin is pulle d low in mast er mo de (see sec t ion 10 .4 .5 .1 mast er mo de fau l t ( m odf) ) . an spi in te rr up t ca n be g ene ra te d if spi e=1 in th e spicsr reg i ste r . this bit is cle a r ed by a so ft war e se que nce (an a c - c e s s to the spicr register while modf=1 fol- lowed by a writ e t o th e spi cr r egist er ). 0: no ma st er mod e fa ult d e t e ct ed 1: a f ault in mast er mo de h a s b een d e t e ct ed bit 3 = reser ved, must b e ke pt cle a re d. bi t 2 = sod spi ou tp ut dis ab le. this bit is set a nd clea re d by sof t war e . when se t, it disable s t he alt e r n a t e f u n c t i on o f t he spi ou tp ut (mo s i in mast er m ode / mi so in sla v e m ode ) 0: spi o u t put en able d (if spe=1) 1: spi o u t put disab l ed bi t 1 = ssm ss ma na geme n t . this bit is set a nd clea re d by sof t war e . when se t, it disable s the alternate function of the spi ss pin and u s es t h e ssi bit value inste ad. see section 10. 4. 3. 2 slave sele ct man age men t . 0: ha rd ware management (ss m a na ge d by e x t er - n a l pin) 1: sof t w are m ana ge ment ( i n t e r na l ss signal con- trolled by ssi bit. external ss pin f r ee f o r g ene r- al- p ur po se i / o ) bi t 0 = ssi ss in te rn al mod e . this b i t is set a nd cl ear ed by so ft war e . i t act s as a ?c hip s e lect? by controlling the level of the ss sl a ve se lect signa l wh en t he ssm bit is set . 0: sla v e se lect ed 1: sla v e dese l ecte d data i/ o regi st er (spi dr) re ad/ writ e r e s e t value: undefined the spi dr re gist er is used to t r ansmit and re ce ive dat a o n t he se rial b u s. in a ma st er de vice, a wr ite to this register w ill init iate transmission/reception of a not he r byt e . not e s : during the last c l oc k cycle the spi f bit is se t, a co py of t h e r e ceived dat a byte in th e shif t reg i st e r is mo ve d t o a buf f e r . whe n th e user r e a d s th e ser i al pe riph er al dat a i/ o r egist er , th e buf f e r is a ct u a lly be in g r e ad . w h ile the spif bit is s e t, all writes to the spidr reg i st e r ar e in hibit e d un til t h e spi c sr r e g i st er is rea d . wa rning: a writ e t o t he spi dr re gist er p l aces dat a d i rect ly in to th e shif t r egist er fo r t r a n smissio n . a re ad t o t h e spi dr re giste r re tu rns th e va lue lo- ca te d in th e b u f f e r a nd not t h e cont en t o f th e shif t r e gis t er ( se e f i gur e 46 ). 70 spif wcol ovr m od f - sod s sm s s i 70 d7 d6 d5 d4 d3 d 2 d1 d0 1 st72324jx st72324kx 89/164 s e ria l periphera l inter f a c e (cont ?d ) tabl e 19 . spi reg i s t er m a p and res e t val u e s address (hex.) register label 7 65432 10 0021h spidr reset value msb xxx xx xx lsb x 0022h spicr reset value sp i e 0 spe 0 spr2 0 mstr 0 cpo l x cp h a x spr1 x spr 0 x 0023h spicsr reset value spif 0 wc o l 0 or 0 modf 00 sod 0 ss m 0 ssi 0 1 st72324jx st72324kx 90/164 10.5 serial c o mmunications inter f a c e (sci) 10.5.1 int r oduc tion the seria l commu nicat i on s i n t e r f ace ( s ci ) o f fe rs a fle x ib le mea n s o f f u ll- dup lex d a t a exchan ge with exte rn al equ ipme nt req u ir ing a n indu st r y sta n d a rd nrz asynchro no us ser i al dat a f o r m at . th e sci o f - fe rs a very wide r ang e of ba ud r a t e s u s ing t w o bau d ra te g ene ra to r syst ems. 10. 5. 2 ma in fe at ures full du plex, a s ynchr o n ous commu nicat i on s nrz sta nda rd f o r m at (ma r k/ space) du al bau d ra te g ene ra to r syst ems in dep end ent ly p r o g ra mma b le tr an sm it and receive b aud r a t e s up t o 500 k b aud pr og ra mmab l e dat a wor d len g t h (8 o r 9 bit s ) re ce ive bu ff er f u ll, tr ansmit bu f f e r e m pt y and e n d o f t r an sm iss i on f l ag s two r e ceiver wa ke -u p mod e s: ? a ddr ess b i t ( m sb) ? i dle line mut i ng fu nctio n f o r mu ltip ro ce ssor conf igu r a t io ns se par at e ena ble bit s f o r tr ansmit t e r and re ce i v e r four er ror det ect i on f l ag s: ? o verrun error ? n oise error ? f ra me er ro r ? p ar ity err o r five in t e rr up t sour ces wit h fl ags: ? t ra nsmit d a t a re gist er em pt y ? t ra nsmissi on comp let e ? r e c eive dat a r egist er f u ll ? i dle line received ? o ver r u n er ror det ect e d pa ri t y c o n t r o l : ? t ra nsmit s p a rit y b i t ? c h e cks pa rit y o f re ceived da ta b y te re duced p o wer con s umpt io n mode 10. 5. 3 ge ner a l des c ri pt ion the in te rf ace is ext e rn ally co nne cte d to ano th er device by t w o pin s (se e figu re 2. ): ? tdo: t r a n s m it dat a ou tp ut . whe n th e tr an smit - t e r and th e rece ive r ar e disab l ed, th e out pu t p i n r e t u r n s to it s i / o po rt co nf igur at ion . when t h e t r ansmit t e r a nd/ or th e re ce ive r ar e en able d and no th ing is to b e tr an sm itt e d , the td o p i n is at high lev e l. ? rdi: rec e iv e data input is t he se ria l da ta inp u t . ove r sa mp lin g tec h n i q u e s ar e us ed fo r d a t a r e - co ve ry by discr i mina t i ng be t w e en valid in coming d a t a an d noise . through th ese pin s , se ria l d a t a is t r a n smit te d and receive d as f r ames compr i sing: ? an id le lin e prio r t o tr an sm ission o r re cept ion ? a st ar t bit ? a da ta wo r d (8 o r 9 b i ts ) le a st sig n if ican t bit fir st ? a st op b i t ind i ca t i ng t hat th e fr am e is comp let e this int e r f ace u s e s two typ e s of b aud ra te ge ne rat o r : ? a con v e n t i on al type f o r co mmo n ly-use d bau d ra te s ? an e x t e n ded t ype with a pr escaler o f f e r i ng a ver y wid e ra nge of bau d ra te s e v e n with non -st and ard osc illator frequencies 1 st72324jx st72324kx 91/164 serial communications interface (cont?d) figure 53. sci block diagram wake up un it re ceive r cont rol sr tr a n sm it c ontr o l tdre tc rdrf idle or nf fe pe sci control in terr u pt cr 1 r8 t8 scid m wake pce ps pie received data register (rdr) received shift register read transmit data regis t er (td r ) transmit shift register write rdi td o (data register) dr t rans m itte r cl ock re ceive r c l ock rece iv er ra te tr a n sm it t e r r a te br r sc p 1 f cpu c ontr o l c ontr o l scp 0 sct2 s c t1 s c t0 sc r2 scr1 scr0 /pr /1 6 c onve ntiona l ba ud rat e ge nera tor sb k rw u re te il i e ri e tcie tie cr2 1 st72324jx st72324kx 92/164 s e ria l commun ica t ion s in terface (c on t?d ) 10. 5. 4 fu nct i on al des c ri pt io n the block diag ra m of t he se rial con t rol i n t e r f ace, is shown in fig u r e 1. i t co nt ains six de dicat ed r eg- is ters: ? two control regis t ers (sc i cr1 & scicr2) ? a status regist er (scis r ) ? a b a u d rat e r egist er ( s ci brr) ? an e x te nde d pr escaler re ce iver r e g i st er (sci er- pr ) ? an ext e n ded pre s ca ler t r a n smit te r r egist er (sci- et p r ) r e f e r to th e r e g i st er de sc rip t io ns in se ctio n 0. 1. 7 fo r t he de fin i tio n s of e a ch bit . 10. 5. 4. 1 seri a l data format wo rd le ng th m a y be sele ct ed as bein g eit h e r 8 or 9 bit s by p r o g ra mmin g t h e m bit in th e sci c r1 re g- is te r (se e fig u r e 1. ). the tdo pin is in low st at e d u rin g t he sta r t bit . the tdo pin is in hig h st at e d u rin g t he sto p bit . an i d le ch ar acte r is int e r p re t ed as an en tir e fr ame of ? 1 ? s f o llowed b y t h e st ar t b i t o f t h e next fr ame wh ich con t a i ns dat a. a br ea k cha r ac ter is in te rp re te d on r e ceiv ing ? 0 ?s fo r some mult ipl e of t he f r ame per iod . at t he end of th e last b r e a k f r ame t h e tr ansmit t e r in sert s an ex- tr a ?1 ? bit to a c kno w l edg e th e st ar t b i t. t r an sm iss i on a n d r e c e p t io n ar e d r iv en b y t h e i r own bau d ra te g ene ra to r. figure 54. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bi t 7 bit8 st a r t bit stop bit nex t st a r t bi t idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit ne x t st a r t bit st a r t bit idle frame start bit 9-b i t wor d le ngth ( m bit is set ) 8- bit word lengt h (m bit is re set ) possible parity bit possible parity bit break frame st a r t bit extra ?1? da ta fra m e break frame start bit extra ?1? da ta fra m e ne xt da ta f r am e next data frame 1 st72324jx st72324kx 93/164 s e ria l commun ica t ion s in terface (c on t?d ) 10. 5. 4. 2 tr ansmi t ter the t r a n smit te r can send d a t a wor d s o f eit h e r 8 or 9 bit s de pen din g on t he m bit sta t u s . whe n t he m bit is set , wo rd len g t h is 9 bit s an d t h e 9t h bit (t he msb) has t o be st ore d in th e t 8 b i t in t he sci c r1 regist er. ch arac te r tran smis si on d u r i ng an sci tr an sm iss i on , da ta sh ifts o u t le a s t s i gn ific an t b i t fir s t o n t h e tdo pin . in th is m o de , th e sci d r r egist er co nsist s o f a b u f f e r ( t dr) be- twee n t he int e r n a l bus and th e tr an sm it shif t r e g i s- te r (see f i gur e 1. ). pr oce dure ? sele ct th e m bit t o de fin e t he wor d leng th . ? sele ct th e desir ed ba ud r a t e using t h e sci b rr and t h e sci e tpr r egist er s. ? set t he te bit t o assign t h e t d o pin t o t he a l te r- nat e f unct i on a nd t o se nd a id le fr ame a s f i rst tr an smission . ? access t h e scisr re gist er and writ e t h e dat a to se nd in t he scidr r e g i st er ( t his seq uen ce cle a rs th e tdre bit ) . re pe at t h is se qu ence f o r e a ch dat a t o be t r a n smit te d. c l ea rin g th e t dre b i t is alwa ys pe rf or m e d by th e f o llo win g so ftw ar e se qu e n c e : 1 . an ac ce ss to th e scis r r e g i st er 2. a writ e t o th e sci d r r egist er the tdre b i t is se t by har dwar e an d it ind i ca t e s: ? t h e t d r r e g i st er is em p t y. ? t h e d a t a tr an sf er is be g i nn in g. ? t h e ne xt da ta ca n b e writ te n in th e s c idr re gis - te r with out over wr it ing t he pr eviou s da ta . this fla g gen er at es a n int e r r u p t if th e tie bit is set and the i bit is cleared in the ccr regis t er. wh en a t r a n smissio n is t a king p l ace, a wr ite in- st r u ctio n t o t h e sci d r r e g i st er sto r es t h e dat a in th e tdr re gist er and which is copie d in th e shif t re giste r at th e end o f t h e cur r e n t t r ansmission. wh en no tr ansmission is ta kin g place , a writ e in- st r u ctio n t o t he sci d r re gist er pla c e s t he dat a di- re ct ly in th e sh if t r egist er , t he d a t a t r an sm ission st ar t s , and t h e t d re bit is imme diat ely se t. wh en a fr ame tr an smi s sion is comp let e ( a f t e r t h e st op bit ) th e tc b i t is set a nd a n in te rr upt is g ene r- at ed if t h e tci e is se t and t he i bit is cle a r ed in t h e c cr regis t er. cle a ri ng th e tc b i t is pe rf or med b y t he fo llowing so ft war e se que nce: 1. an a c cess t o t he scisr re giste r 2. a writ e to t h e sci d r re gist er not e : th e tdre and tc bit s ar e clea re d by t h e sa me sof t war e sequ ence. bre a k char act ers s e t t ing th e sbk b i t lo ad s th e s h ift r e gis t er with a bre a k cha r a c t e r . th e bre a k f r ame le ngt h de pen ds on t he m bit (see fig u r e 2. ). as lon g as th e sbk bi t is set , th e sci send b r e a k fr ame s t o t h e tdo pin . af te r clea rin g t h is bit by so ft war e th e sci in se rt a log i c 1 bit a t t h e end of th e last b r ea k f r a m e t o gu ar ant ee t h e reco gnit i on of t h e st ar t bit of t h e next f r a m e. idl e char act ers se tt in g t he t e bit dr ive s t h e sci t o sen d a n idle fr ame b e f o r e th e fir s t da ta f r ame . cle a ri ng an d t hen se tt ing th e te bit dur ing a tr ans- missio n se nds an id le fr ame a f t e r th e curr en t wor d . not e : reset t in g a nd se tt ing t he te bit causes t h e dat a in t h e tdr r egist er t o b e lo st . th er ef or e t h e best t i me t o t ogg le t he te bit is when t h e t d re bit is s e t , th at is , be fo re wr iting the nex t by te in the sc i d r . 1 st72324jx st72324kx 94/164 s e ria l commun ica t ion s in terface (c on t?d ) 10. 5. 4. 3 rec e i ver the sci can rece ive dat a wo rd s o f eit her 8 o r 9 bit s . whe n t he m bit is set , wo rd leng th is 9 bit s and t h e msb is st or ed in t he r8 b i t in t he sci c r1 regist er. ch arac te r rece pt ion du rin g a sci r e cep t io n, da ta s h ifts in leas t signifi- c a n t bit fir s t t h r o ug h th e rdi pin . in th is m o de , th e sci d r r e g i st er con s ist s or a bu ff e r ( r dr) be- twee n th e in te rn al b u s a nd t he re ce ive d sh ift r e g i s- te r (see f i gur e 1. ). pr oce dure ? sele ct th e m bit t o de fin e t he wor d leng th . ? sele ct th e desir ed ba ud r a t e using t h e sci b rr a n d th e scier p r r e gis t er s. ? set t h e re bit , t h is ena ble s t he re ceiver which beg ins sea r chin g f o r a sta r t bit . wh en a cha r act e r is re ce ive d : ? the rdrf b i t is set . i t ind i ca te s t hat th e co nt en t o f th e sh ift r e gis t er is tr an sf er re d to th e rd r. ? an int e r r u p t is gen er at ed if t h e rie bit is se t and th e i bit is clea red in th e ccr r e g i st er . ? the er ro r fla g s can be set if a fr am e e r r o r , noise or an over ru n er r o r has b een de te cte d d u rin g r e - ce pt ion. cle a r i ng t he rdrf bit is pe rf or med b y t he f o llowing so ft war e se que nce do ne by: 1 . an ac ce ss to th e scis r r e g i st er 2. a re ad t o t he scidr r e g i st er . the rdrf bit mu st b e cle a r ed bef or e th e e n d of t h e re ce pt ion of t h e n e xt ch ar acte r to a v o i d a n over run er ror . br eak cha r act er wh en a br ea k ch ara c te r is r e ceived, t h e sci h an- dles it as a f r am ing er ro r. id le cha r act er wh en a id le f r ame is de te ct ed , t her e is t h e same pr ocedu re as a dat a re ce ive d cha r a c t e r p l us an in- te rr upt if t h e i l i e b i t is se t an d th e i bit is clea red in t h e c cr r e gis t er . overrun erro r a n ov er ru n e r r o r o c c u r s wh en a ch ar ac te r is re - c e iv ed wh e n rdr f ha s no t be en r e set . d a t a ca n not be t r a n sf err e d f r om t he shif t r e g i st er to t h e r dr r e g i st er as lo n g a s th e r drf bit is no t cl e a re d. w h e n a n ov er ru n er ro r oc cu rs: ? th e or bit is se t. ? the rdr content is not lost. ? t h e sh ift r e gis t er is o v er wr itte n . ? an int e r r u p t is gen er at ed if t h e rie b i t is se t a n d t h e i bit is clear ed in t h e ccr r e g i st er . the o r bit is r e set by a n access to th e scisr re g- ist e r f o llowed by a sci d r r egist er r e a d ope ra tio n . noi s e er ror o v e r sam p lin g t e c h n i q u e s ar e us ed fo r d a ta r e co v- ery by d i scrim i nat ing be twee n valid incomin g da ta and noise. nor m al da ta bit s a r e co nsider ed va lid if th ree co nsecut ive sample s ( 8 t h , 9t h, 10t h ) ha ve th e sa me bit valu e, o t h e r w ise t he nf f l ag is se t. in th e case o f st ar t bit de te ctio n, t he nf fla g is set on th e b a sis of an alg o r i th m comb inin g b o t h valid edg e de te ct io n an d t h r ee sam p les ( 8 t h , 9t h, 10t h) . ther ef or e, to pre v e nt th e nf f l a g get t i ng set dur ing st ar t b i t r e cep t io n, th er e shou ld be a va lid ed ge d e - tec t ion as well as three v a lid s a mples . when no ise i s de te ct ed in a fr ame : ? the nf f l ag is set at t h e rising e dge of t h e rdrf bit. ? da ta is tr an sf er re d fr om t h e s h ift r e g i ste r to th e scid r regist er. ? no in te rr upt is ge ner at ed . however t h is b i t rises at the same time as th e rdrf bit which its e lf ge ne r a te s an in te rr u p t. the nf f l ag is r e set by a sci s r reg i st e r re ad o p - era t io n f o llo we d by a sci d r r egist er rea d o per a- tio n . du ring re ce pt ion, if a f a lse sta r t bit is d e t e cte d ( e . g . 8t h, 9t h, 1 0 t h sa mple s are 01 1, 10 1, 110 ), t h e fr ame is discar ded a nd th e r e ceiving sequ en ce is not sta r t e d f o r th is fr ame . ther e is n o rdrf bit set fo r t h is fr ame and th e nf f l ag is set in t e rn ally (n ot acc e s sible to the user). this nf flag is acc e s sible alon g wit h t he rdrf bi t whe n a ne xt valid fr ame is receive d . n o te : if t he ap plicat ion st ar t bit is n o t long eno ugh to mat c h th e a bove r eq uire m en ts, th en t he nf flag ma y g e t se t du e t o th e shor t st ar t bit . i n t h is ca se , th e nf fla g m a y be ig nor ed by t h e ap plica- t i on s o f t wa re w h e n th e fir st v a lid b yt e is r e c e iv ed . se e also sect ion 0. 1. 4. 10 . 1 st72324jx st72324kx 95/164 s e ria l commun ica t ion s in terface (c on t?d ) figure 55. sci baud rate and extended prescaler block diagram t rans mitte r receiver scietpr scie rpr extended prescaler receiver rate control ext end e d pre s ca le r t r an smitt e r rat e cont rol ext ende d pre s ca ler cl ock clock receiver rate tra nsmitt e r ra te scibr r scp 1 f cp u co ntro l con trol sc p0 sc t 2 sct 1 sct 0 scr2 sc r1 sc r0 /pr /16 con ven tional b aud rat e gen e rat or extended receiver prescaler register e x t e nde d tra nsmitt e r pr esca l e r regist er 1 st72324jx st72324kx 96/164 s e ria l commun ica t ion s in terface (c on t?d ) framing error a fr am in g er ro r is d e t e c te d wh en : ? the sto p bit is n o t r e cog n ized on r e cept io n a t t he expect ed t i me, fo llowing e i th er a d e - s ynchr o n i - z a t ion or ex cessive noise. ? a br ea k is r e c e iv ed . w h e n th e fr am in g er ro r is d e t ec te d: ? th e fe b i t is se t by h a r d w a r e ? da ta is tr an sf er re d fr om t h e sh ift re g i ste r to th e sci d r re gist er. ? no in te rr up t is ge ner at ed . however t h is b i t r i se s at the same time as th e rdrf bit which its e lf gen er at es a n int e r r u p t . the fe bit is reset by a scisr r e g i st er rea d ope r- at ion f o llo we d by a sci d r re giste r r ead ope ra tio n . 10. 5. 4. 4 conv ent i o n al ba ud ra te g ene rat i o n the ba ud rat e fo r th e r e ceiver an d tr ansmit t e r (rx and tx) a r e se t inde pen de nt ly a n d ca lcu l at ed as follows : wi t h : pr = 1 , 3, 4 or 1 3 (see scp[1 : 0] b i ts) tr = 1, 2 , 4, 8, 1 6 , 32, 64, 12 8 (see sct[ 2: 0] b i t s ) rr = 1, 2, 4, 8 , 16 , 32 , 6 4 , 128 ( se e scr[ 2: 0] b i ts) al l t h e s e b i ts ar e in th e sci b rr r egist er . ex ampl e: if f cpu is 8 mhz ( n o r ma l mo de) and if pr = 1 3 an d tr = r r = 1, t he t r a n smit and r e - ce ive b a u d rat e s ar e 38 400 b aud . no te: the bau d r a t e re gist ers must not be ch ang ed while t h e t r ansmit t e r o r th e re ce iver is en- able d . 10. 5. 4. 5 ext e nd ed baud rat e gen e ra ti on the ext e n ded pr escaler o p t i on gi ve s a ve ry f i ne tu ning on t h e bau d r a t e , using a 255 va lue p r e s cal- er , wh er eas t h e con v e n t i ona l bau d ra te ge ner a- tor retains indus t ry s t an dard s o ftware compatibili- ty . the e x t e nde d ba ud r a t e ge ner at or block diag ra m is de scr i bed in t h e figu re 3. t h e o u t p u t clo ck ra te se nt t o th e tr an sm itt e r or t o t h e r e c e iv er is th e ou tp ut fr o m th e 16 d i vid e r d i vid - ed b y a f a cto r r a n g ing fr om 1 t o 2 55 set in th e sci- erpr o r t he scietpr re giste r . not e : th e exte nde d pr esca ler is act i va te d by set - tin g t h e sciet p r or sci e rpr re gis t e r to a v a lue ot her t han ze ro . t he b aud ra te s a r e ca lcu l at ed as follows : wi t h : e t p r = 1, .., 25 5 (s ee sc ietpr re gis t e r ) erpr = 1, .. 25 5 (see scierpr r e g i st er ) 10. 5. 4. 6 rec e i ver mu ti ng and wak e - up fea t ur e i n multiprocessor configurat ions it is often des i ra- ble t h at onl y t h e int e n d e d me ssag e r e cipie n t sh ould a c t i vely r e ceive th e fu ll me ssa ge cont en ts, th us r e d u cing re du nda nt sci ser v ice ove r he ad f o r all non a ddr essed r e ceiver s. the no n a ddr essed devices ma y be pla c e d in sle ep mo de by mea n s o f t h e mu tin g f unct i on. se tt in g t he rwu bit by sof t war e p u t s th e sci in sle ep mo de: all t h e r e cept io n st at us bit s can n o t b e se t . a ll the receive interr u p t s ar e inh i bit e d . a mu te d re ce ive r may be awake ned b y on e of t h e following tw o w a y s: ? by idle line detection if the wake bit is reset, ? by address mark detectio n if the w ake bi t is set. re ce ive r wake s- up by i d le line de te ct ion when th e re ceive line h a s re co gnized an i d le f r am e. then th e rwu bit is r e set by har dwar e bu t t h e idle bit is no t set . re ce ive r wa ke s- up by ad dr ess mar k de te ct ion wh en it re ceived a ?1 ? as t he mo st sign if ica n t bit of a wo rd, th us indicat i ng t h a t t he me ssag e is an a d - dre s s. th e r e cep t io n o f th is par ticu lar wo rd wakes up t h e r e ceiver , reset s t he rwu bit a nd se ts t h e r drf bit, w h ic h allow s the receiver to rec e ive this wo rd n o rm ally a nd t o use it a s an a d d r ess wo rd. c aution : in mu te m o de , d o n o t wr ite to th e s c ic r2 re gis t e r . if th e s c i is in m u te m o de d u r in g th e r ead op er at ion (rwu = 1 ) a n d a a ddr ess mar k w a k e u p e ven t o ccu rs ( r wu is r e s e t ) be fo re th e wr ite op era t ion, t he rwu bit is se t a gain by t h is wr ite op era t io n. conseq uen tly t h e add re ss byt e is lo st a n d th e sci is no t wo ke n u p fro m m u te m o de . tx = (1 6 * pr) * tr f cpu rx = (1 6 * pr ) * rr f cpu tx = 16 * etpr*(pr*tr) f cpu rx = 16 * er pr*(pr * r r) f cpu 1 st72324jx st72324kx 97/164 s e ria l commun ica t ion s in terface (c on t?d ) 10. 5. 4. 7 pari ty con t ro l pa rit y co nt ro l (g ene rat i o n of pa rit y b i t in tr an sm is- sio n and p a r i ty ch ecking in re ce pt ion ) ca n be e na- bled by set t i ng t h e pce bit in th e sci c r1 reg i ste r . de pen din g on t h e f r ame le ngt h d e f i ned by t h e m bit , t he po ssible sci f r ame f o r m at s a r e as list e d in tab l e 1 . tabl e 20 . fr ame forma ts lege nd: sb = start bit, stb = stop bit, p b = parity bit no te : i n ca se o f w a k e up b y an ad dr e ss ma r k , th e msb bit of t he da ta is t a ken int o accoun t an d n o t th e par it y bit ev en pa r i t y : t h e p a r i ty bit is ca lcu l at ed t o obt ain an even nu mbe r of ? 1 s? in side th e fr ame ma de of th e 7 or 8 lsb b i ts ( dep en ding on whet he r m is equ al to 0 or 1) and t h e par ity bit . exa m ple : d a t a = 0 0 1 1 010 1; 4 bit s set => pa rit y bit is 0 if ev en parity is s e lected (ps bit = 0). odd pa rity: th e pa rit y b i t is ca lcu l at ed t o o b t a in an odd n u mbe r of ? 1 s? inside t he f r am e m ade of th e 7 or 8 lsb bit s (d epe ndin g on whet he r m is equ al to 0 or 1 ) an d th e par it y bit . exa m ple : d a t a = 0 0 1 1 010 1; 4 bit s set => pa rit y bit is 1 if odd parity is selected (ps bit = 1). tran smission mode : if th e p c e b i t is se t t h e n th e msb b i t of th e da ta wr itt e n in t h e d a t a re gist er is n o t t r a n s m it te d bu t is c h a n g e d by th e pa r i ty bit. re cep tion mode: if th e pce b i t is s e t t h e n th e in - te rf ace checks if t h e r e ceived da ta b y t e ha s an even nu mber o f ?1 s? i f even pa rit y is sele ct ed (ps = 0) or an o dd n u mb er of ?1s? if o dd p a r i ty is s e le ct ed (ps = 1) . if t h e pa r i ty ch e ck fa ils, th e pe fla g is se t in th e sci s r re gist er an d a n int e r r up t is gen er at ed if pi e is set in t h e sci c r1 r egist er . 10. 5. 4. 8 sci clo ck tol er anc e du ring r e cept ion , each bit is sa mple d 1 6 t i mes. the majo rit y of th e 8 t h , 9t h an d 1 0 t h samp les is co nsider ed as t h e b i t va lue. f o r a va lid b i t det ec- tio n , all t he t h r ee sam p les shou ld ha ve th e same va lue ot he rwise t h e no ise f l ag ( n f ) is se t. for ex- ample : if t h e 8t h, 9t h and 10 th sample s ar e 0, 1 and 1 resp ectively, t hen t he bit valu e is ? 1 ? , but t h e no ise fl ag bit is set b e cause t he t h r ee samp les va lues ar e not th e sa me. co nsequ ent ly, t he bit len g t h must be lon g eno ugh so t hat th e 8 t h , 9t h and 1 0 t h sam p les h a ve th e d e - sir ed bit value . this me ans t h e clo c k f r e q u ency sh ould no t var y mor e th an 6/ 16 (3 7. 5%) with i n one bit. the sampling cloc k is resynchroniz e d at eac h st ar t bit , so t h a t wh en re ce iving 10 bit s (o ne st ar t bit , 1 da t a byte , 1 st op bi t) , t h e clock d e viat ion m u st no t ex ce ed 3 . 7 5 % . n o te : th e int e r nal samplin g clo c k of t h e micro c o n - tr oller samp les t he p i n valu e on ever y fa lling edg e. ther ef or e, th e int e rna l sa mplin g clock a nd t h e t i me th e app lica t io n expe ct s t h e sam p ling t o t a ke pla c e may be out of syn c. fo r e x a m ple : i f t he b aud ra te is 15 .6 25 kbau d (b it len g t h is 64 s), t h e n th e 8t h, 9t h and 1 0 t h sa mple s ar e at 28 s, 32 s a nd 36 s respectively (the firs t sample s t arting ideally at 0s). but if the falling edge of the internal cloc k oc- cu rs ju st b e f o r e th e p i n va lue ch an ges, t he sam- ples would th en b e ou t o f sync by ~4 us. t h is mean s t he ent ir e b i t len g t h m u st be at le ast 40 s ( 3 6 s fo r th e 10 th sam p le + 4 s fo r sy nch r on iza - t i on w i th th e int e r n al s a m p ling c l oc k). m bit p c e bit sc i frame 0 0 | sb | 8 bit data | stb | 0 1 | s b | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit d a ta p b | s t b | 1 st72324jx st72324kx 98/164 s e ria l commun ica t ion s in terface (c on t?d ) 10. 5. 4. 9 cl ock dev i a t i on caus es the cau s e s which cont r i but e t o th e to t a l deviat i on ar e: ?d tra : deviat ion d u e to t r an sm itt e r er ro r ( l o c a l oscillator error of the tr ansmitter or the trans - m i tt er is tr an sm itt i n g a t a d i ff er en t ba u d r a te ). ?d qua n t : err o r d u e to t h e ba ud r a t e qu an tiza- tio n of th e re ce ive r . ?d rec : deviation of the lo cal osc illator of the re ce ive r : this de via t io n can occur dur ing t h e re ce pt ion of on e com p let e sci me ssag e a s - su ming t h a t th e deviat i on h a s be en comp en- sa te d at th e beg inn i ng of th e message . ?d tcl : devia t io n du e t o t he t r a n smissio n line (g ene ra lly du e to t h e tr an sceiver s ) al l t h e de via t io ns of th e syst em sho u ld b e ad ded and com par ed t o t he sci clock t o le ra nce: d tra + d quant + d rec + d tc l < 3. 75 % 10. 5. 4. 10 noi s e err o r ca use s se e also de scrip t ion of no ise e r r o r in section 0. 1. 4. 3 . st ar t bi t the no ise fla g (nf) is se t du rin g st ar t b i t re cept ion if on e of t h e f o llowing cond it ions occu rs: 1. a valid falling edge is not detec t ed. a falling e dge i s conside r e d to b e valid if t h e 3 co nsecu- tive samples before t he falling edge oc curs are d e t e cte d a s '1 ' an d, af te r t h e f a lling e dge o c cur s , d u rin g t he sam p ling of t h e 16 sam p les, if one o f th e sa mple s nu mbe r ed 3 , 5 or 7 is de te ct ed a s a ? 1 ? . 2. dur i ng sa mplin g o f th e 16 sa mple s, if o n e of t h e sam p les n u mb er ed 8, 9 or 1 0 is det ect ed as a ?1 ?. ther ef or e, a valid st ar t bit m u st sat i sfy bot h t h e abo ve con d it ion s t o pre v e n t t h e no ise f l ag ge tt ing se t. da ta b i ts the n o ise f l ag ( n f ) is se t d u rin g no rm al dat a b i t r e - ce pt ion if t h e fo llowing cond it ion occur s : ? durin g th e samp ling of 16 samp les, if all th re e sa mples numb e r ed 8, 9 an d10 ar e not t h e same . t he m a jor i t y o f t h e 8t h, 9t h a nd 1 0 t h sam p les is co nsider ed a s t he bit value . ther ef or e, a valid dat a bit must h a ve samp les 8 , 9 and 1 0 at t he same va lue t o pr even t t h e no ise flag g e t t in g se t. figure 56. bit sampling in reception mode rd i l i n e sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16 1 st72324jx st72324kx 99/164 s e ria l commun ica t ion s in terface (c on t?d ) 10. 5. 5 lo w po wer mo des 10. 5. 6 i n te rrup t s the sci int e r r u p t event s ar e conn ect ed t o t h e s a m e in te rr up t ve cto r . these events generate an interrupt if the corre- sponding enable control bit is set and the inter- rupt mask in the cc regist er is reset (rim instruc- tion). mode description wa i t no effe ct on sci. sci interrupts c ause the device to e x it fro m wait mode. halt sci registers are frozen. in halt m ode, the s c i s t ops transmitting/re- ceiving until halt mode is exited . interrupt event event flag enable control bi t ex i t fr om wa i t exit from halt transmit data register em p t y tdre tie y es no transmission com- plete tc tcie yes n o r e c e ive d data ready to be read rdrf rie yes n o over run err o r detec t - ed or yes n o idle line d e tected idle il ie yes n o p a rit y er ror p e p i e yes n o 1 st72324jx st72324kx 100/164 s e ria l commun ica t ion s in terface (c on t?d ) 10. 5. 7 regi st er des c ri pt ion st at us r e g i s t er (s c i sr ) re ad on ly re se t valu e: 1 10 0 000 0 (c0h ) bit 7 = tdre tr an sm it da ta r e g i st er e m pt y. t h is bit is s e t b y ha rd wa r e wh en th e co nt en t o f th e tdr re giste r has bee n tr an sf er re d int o t h e shif t r e g i st er . an in te rr up t is ge n e r a t e d if th e t i e bit = 1 in th e sci c r2 r egist er. it is cle a r ed by a sof t w are se que nce (a n a c ce ss t o t he sci s r r egist er f o l- lowed by a writ e t o th e sci d r r egist er ). 0: dat a is not tr an sf er re d to t h e sh ift re giste r 1 : da ta is t r a n sfe rr ed t o th e shif t r e gist er no te: da ta is no t tr an sf er re d t o th e s h if t re gis t e r unle s s th e tdre bit is clea red . bi t 6 = tc tr ansmission comp let e . this bit is se t by har dwar e wh en t r a n smissio n of a f r a m e co n t ain i n g da ta is co mp le te . an in te rr up t is gen er at ed if tci e = 1 in t h e sci c r2 r egist er . i t is cle a r ed by a sof t w a r e sequ en ce ( an access t o t h e sci s r re gist er f o llowe d b y a writ e to t h e scidr re giste r ) . 0: t r an sm ission is no t comp let e 1: t r an sm ission is comp let e no te: tc is no t se t a f t e r t he tr an sm ission of a pr e- amb l e or a br eak. bi t 5 = rdr f received dat a re ad y f l ag. t h is bit is s e t b y ha rd wa r e wh en th e co nt en t o f th e r dr r e g i st er ha s b e e n tr an sf er re d t o t h e sci d r re giste r . an int e r r u p t is g ene ra te d if ri e = 1 in t h e sci c r2 re giste r . i t is clea re d by a so ft war e se- que nce (a n acce ss to t h e sci s r re giste r f o llowed b y a re ad t o th e s c id r r e g i st er ). 0 : da ta is n o t r e c e iv ed 1: receive d dat a is r e a d y t o be rea d bi t 4 = idle id le lin e d e t e c t. this bit is set by ha rd wa re wh en a i d le line is de- te ct ed . an int e r r u p t is g ene ra te d if t he i l i e = 1 in th e sci cr2 re giste r . it is cle a re d by a sof t wa re se- que nce (a n acce ss to t h e sci s r re giste r f o llowed b y a re ad t o th e s c id r r e g i st er ). 0: no i d le l i ne is d e t e ct ed 1: i d le l i ne is det ect e d n o te : th e idle bit is no t set ag ain un til th e rdrf bit has be en se t it self (t ha t is, a n e w idle lin e oc- cu rs). bi t 3 = or over ru n er ro r. this bit is set by h a r d war e when t h e wo rd cu rr ent ly bein g r e ceived in t h e shif t reg i ste r is r ead y to be transferred into the rd r register while rdr f = 1. a n in te rr up t is ge ne r a t ed if rie = 1 in the sc icr 2 reg i st e r . i t i s clea re d b y a sof t w a r e se que nce ( a n a cc e s s t o t h e sc isr re gis t e r f o llo we d by a re ad t o th e sci d r re gist er) . 0: no over ru n er ro r 1: o v e r r un er r o r is d e t e ct ed not e : whe n th is bit is set rdr r egist er cont e n t is not lost bu t t h e shif t r e g i st er is over writ te n. bi t 2 = nf no i se fl a g . this b i t is set by h a r d war e wh en no ise i s de te ct ed on a re ceived fr ame . it is clear ed by a so ft war e se- que nce (a n acce ss to t h e sci s r re giste r f o llowed b y a re ad t o th e scid r r e g i st er ). 0: no no ise is de te ct ed 1: noise is detected not e : this b i t d oes not gen er at e int e r r u p t a s it a p - pea rs a t th e sam e t i me as t h e rdrf bit which it - se lf ge ner at es an int e rr upt . bi t 1 = fe fr amin g er ror . this bit is set by har dwar e when a de -syn chro niza- tio n , exce ssive n o ise o r a br eak char act e r is d e - te ct ed . i t is clear ed by a so ft war e seq u e n ce ( a n a cc e s s t o t h e sc isr re gis t e r f o llo we d by a re ad t o th e sci d r re gist er) . 0: no fr amin g er ror is de te cte d 1: fr am ing er ro r or b r e a k ch ara c t e r is de te cte d not e : this b i t d oes not gen er at e int e r r u p t a s it a p - pea rs a t th e sam e t i me as t h e rdrf bit which it - se lf g e n e ra te s an int e r r up t. i f th e wor d cu rr ent ly bein g t r ansf e rr ed cause s bot h fr ame er ro r and overrun error, it will be tr ansferred and only the or bit will be set. bi t 0 = pe p a r i ty er ro r. this bit is set by h a r d war e when a par it y er ro r oc- cu rs in re ce ive r mode . it is clea re d b y a sof t w a r e se que nce (a r ead t o t he sta t u s r egist er f o llo we d by an a c cess t o t he sci d r d a t a r egist er ). an in te r- r u pt is ge ne r a t e d if pie = 1 in th e sci c r1 reg i st er . 0: no pa rit y e r r o r 1: par i t y er ro r 70 td re tc rdr f i dl e o r n f f e p e 1 st72324jx st72324kx 101/164 s e ria l commun ica t ion s in terface (c on t?d ) co nt ro l re g i s t e r 1 (s c i c r 1 ) re ad/ writ e re se t valu e: x0 00 00 00 ( x 0 h ) bi t 7 = r8 receive da ta b i t 8. this b i t is used t o st or e t he 9t h bit of th e r e ceived wo rd w h e n m = 1. bi t 6 = t8 t r an sm it da ta b i t 8. this bit is used t o sto r e t he 9 t h bit of t h e tr an sm it- te d wo rd whe n m = 1. bi t 5 = scid dis abled for low p o wer co nsump t io n wh en t h is bit is set th e sci pr escaler s a nd o u t put s ar e st op ped a nd t h e e nd of th e cu rr en t byt e tr an s- fe r in or der to r e d u ce power co nsump t io n. this bit is se t an d cle a r e d b y so ftw ar e. 0: sci e nab led 1: sci p r e s cale r an d out pu ts disab l ed bi t 4 = m wo rd le ng th . this bit det er mine s t h e wor d le ngt h. it is set or cle a r ed by so ft war e . 0 : 1 sta r t bit , 8 d a t a bits , 1 s top b i t 1: 1 st ar t b i t, 9 da ta b i t s , 1 st o p bit no te : th e m bit must not be mod i fie d du rin g a da ta tr an sf er ( b o t h t r ansmission an d re ce pt ion ) . bi t 3 = wak e wake- u p me t hod . this bit det er min e s t h e sci wake- u p m e t hod , it is se t or cle a re d by so ft war e . 0: i d le l i ne 1 : ad dr es s m a rk bi t 2 = pce pa rit y con t r o l en able . this b i t select s t he ha rd wa re pa rit y con t r o l (g ene r- at ion and d e t e ctio n) . wh en t he pa rit y cont r o l is e n - able d , th e comp ut ed par ity is inser t ed a t t h e msb posit ion (9 th b i t if m = 1; 8t h b i t if m = 0 ) and pa rit y is che ck e d on th e r e c e iv ed da ta . t h is bit is s e t a n d c l ea r e d b y so ft wa re . on ce it is se t, pce is a ctiv e af te r th e cu rr ent byte ( i n re ce pt ion an d in tr an smis- si o n ). 0: par i t y cont r o l disab l ed 1: par i t y cont r o l ena ble d bi t 1 = ps p a rity sel e ct ion. this bit select s t h e od d or even pa rit y wh en t h e par ity gen er at ion/ de te ctio n is ena bled ( p ce bit se t) . it i s se t and clear ed by sof t w are . the pa rit y is s e le ct ed a ft e r th e cu rr en t by te . 0: even p a rit y 1: o dd pa rit y bi t 0 = pie pa rit y int e rr upt ena ble. this bit e nab les th e int e r r u p t cap abil i ty of t h e har d- wa re par it y con t r o l wh en a pa rit y err o r is de te ct ed ( pe bit se t) . it is se t a n d clea r e d b y s o f t wa re . 0: par i t y er ro r int e r r u p t disable d 1: par i t y er ro r int e r r u p t ena bled . 70 r 8 t8 s c id m wake pce p s p ie 1 st72324jx st72324kx 102/164 s e ria l commun ica t ion s in terface (c on t?d ) co nt ro l re g i s t e r 2 (s c i c r 2 ) re ad/ writ e re se t valu e: 0 0 0 0 000 0 (0 0 h ) bi t 7 = tie tra n smit te r int e r r u p t ena ble . this bit is se t an d clear ed b y sof t war e . 0 : in te rr up t is in hib i te d 1: an sci in te rr upt is ge ne rat e d wh ene ve r tdre=1 in th e sci s r r egist er bi t 6 = tcie tr an sm ission co mple te in t e rr up t e na- ble this bit is se t an d clear ed b y sof t war e . 0 : in te rr up t is in hib i te d 1: an sci int e r r up t is ge ne rat e d whe neve r tc=1 in th e scis r r e g i st er bi t 5 = rie receiver interrupt enable . this bit is se t an d clear ed b y sof t war e . 0 : in te rr up t is in hib i te d 1: an sci in te rr upt is ge ne rat e d wh ene ve r or=1 or rd rf=1 in the scisr regis t er bi t 4 = ilie id le lin e in te rr up t en ab le . this bit is se t an d clear ed b y sof t war e . 0 : in te rr up t is in hib i te d 1: an sci int e r r up t is g ene ra te d whe n e v e r idle=1 in th e scisr r e g i ste r . bi t 3 = te tr ansmit t e r e nab le. this bit ena ble s t h e tr ansmit t e r . i t is set and cle a r ed by so ft war e . 0: t r an sm itt e r is disab l ed 1: t r an sm itt e r is en able d not e s : ? durin g tr an sm ission , a ? 0 ? p u lse on t h e te bit ( ? 0 ? f o llowed b y ? 1 ? ) se nds a p r e a mb le ( i dle lin e) a f te r th e c u rr en t wor d . ? when te is se t t her e is a 1 b i t- t i me de lay b e f o r e t h e tr an smission st art s . c aution: the tdo pin is f r ee f o r ge ner al pu r- pose i / o only when th e te an d re b i ts ar e bo th c leared (or if te is never set ) . bi t 2 = re re ce ive r en able . this b i t en able s th e re ce ive r . i t is set a n d clear ed b y so ftw ar e. 0: receiver is disab l ed 1: receive r is e nab led an d be gins sear ch ing f o r a st art bit bi t 1 = rwu receiver wake-up. this b i t de te rmi nes if th e sci is in mut e mo de or not . i t is set and cle a re d by so ft war e an d ca n be cle a re d by h a r d war e wh en a wake- up sequ ence is recognized. 0: receiver in ac tive mode 1: receiver in mute mode not e : be fo re s e le ctin g m u te m o de (s ett i ng th e rwu b i t) , t he sci must r e ceive some da t a f i r s t , ot her wise it can n o t f unct i on in mut e mo de with wa ke -u p by id le line d e t e ctio n. bi t 0 = sbk sen d br eak. this bit set is used t o send br ea k cha r a c t e r s. i t is se t an d cle a r ed by sof t war e . 0: no br ea k char act e r is tr an smit t e d 1: br eak ch ar acte rs ar e tr an smit t e d not e : if the sbk bit is set to ?1? and then to ?0?, the transmitter sends a break word at the end of the cu rr ent wo rd . 70 tie t cie r ie il ie te re rwu sbk 1 st72324jx st72324kx 103/164 s e ria l commun ica t ion s in terface (c on t?d ) d a ta r egister (scidr) re ad/ writ e r e s e t value: undefined co nt ains t he received o r tra n smit te d da ta cha r - acte r, dep end ing o n whet he r it is re ad f r o m or wr it- te n to . the dat a r eg i st er pe rf or ms a dou ble f un c t i on (r ead and wr ite ) sin c e it is comp osed of two re gist ers, one f o r tr ansmission ( t dr) a n d o ne f o r r e cept ion (rdr ). t h e t d r r e gist er pr ov ide s th e p a r a llel in te rf ac e bet ween th e int e r nal b u s a nd t h e o u t put shif t r eg- is ter (see fig u r e 1. ). the rdr r e g i st er pr ovide s the parallel interfac e bet ween t he inpu t sh ift r e g i st er a nd t h e int e rna l bus (see f i gur e 1. ). b aud rate register (sc i br r) re ad/ writ e re se t valu e: 0 0 0 0 000 0 (0 0h) bi ts 7: 6 = scp[ 1: 0] first sci prescaler the s e 2 pr esca ling bit s allo w se ve ra l sta n d a rd clo c k division ra ng es: bi t s 5 : 3 = sct[2:0] sci tra n smit te r ra te d i vi so r these 3 bit s , in con j unct i on wit h t h e scp1 & scp0 bit s def ine t he to t a l d i vision ap plie d t o th e b u s c l oc k to yield th e t r a n s m it r a te c l oc k in co n ve n t i on - al ba ud rat e ge ner at or mod e . bi t s 2 : 0 = scr[ 2: 0] sci receiver rate divisor. these 3 bit s , in conju n ct ion wit h th e scp[ 1: 0] bit s def ine t h e t o t a l division a pplie d to t h e b u s clo c k to y i eld th e re ce ive r a t e cl ock in co nven tio nal baud ra te g ene ra to r mod e . 70 dr 7 dr6 d r5 dr 4 dr3 d r2 dr1 dr 0 70 sc p1 scp0 sct2 s c t1 sc t0 scr2 s cr1 s cr0 pr prescaling factor scp1 scp 0 10 0 30 1 41 0 13 1 1 tr dividing factor sct2 sc t1 sct0 10 0 0 20 0 1 40 1 0 80 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 rr dividing factor scr2 sc r1 s cr0 10 0 0 20 0 1 40 1 0 80 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 1 st72324jx st72324kx 104/164 s e ria l commun ica t ion s in terface (c on t?d ) e x te nded rece ive pr escaler div i sion r e gister (scierpr) re ad/ writ e re se t valu e: 0 0 0 0 000 0 (0 0 h ) al lows se tt ing of t h e exte nde d pr esca ler r a t e d i vi- sio n fa ct o r fo r t he r e ceive cir c uit . bi ts 7: 0 = erpr [7:0] 8- b i t ex te nd ed r e c e iv e p r escaler r e gister. the exte nde d bau d rat e ge ne rat o r is activat e d wh en a value dif f e r e n t f r om 00h is st or ed in t h is re giste r . th er ef ore t h e clock fr eq uen cy issued fr om t h e 16 divider (se e fig u re 3. ) is divid ed b y t h e bina ry f a ct or se t in t h e sci e rpr reg i st e r ( i n t h e ra nge 1 t o 25 5) . the e x t e n ded bau d ra te g e n e ra to r is not used a f - te r a re se t . e x tended tr ansmit p r esca l e r div i sion r e gister (scietpr) re ad/ writ e re se t valu e: 000 0 00 00 (0 0 h ) a llow s se ttin g of th e ex te rn al pr e sca ler ra te d i vi- s i on f a c t o r f o r th e tr an sm it cir c u i t. bi t s 7: 0 = etpr [7:0] 8- bit ext end ed tra n smit p r escaler r e gist er. the e x t e nde d bau d rat e ge ner at or is a c tivat e d wh en a va lue dif f e r e n t fr om 00h is st or ed in t h is reg i st e r . th ere f ore t he clo c k fr equ en cy issued fr om t h e 16 divider (see figu re 3. ) is divide d b y t h e bina ry fa ct o r set in t he sciet p r r egist er ( i n t h e r a ng e 1 to 2 5 5 ) . the extended baud rate generator is not used af- ter a reset. tabl e 21 . baud rat e sel ect i o n 70 er p r 7 erpr 6 er pr 5 er p r 4 erpr 3 er pr 2 er p r 1 er pr 0 70 etp r 7 e tpr 6 et pr 5 etp r 4 et pr 3 etp r 2 e tpr 1 etp r 0 sym bol param e ter conditions standard baud rate unit f cp u accuracy vs standard prescaler f tx f rx communication frequenc y 8 mhz ~0.16% conventional m o de tr (or rr)=128, pr=13 tr (or rr)= 32, pr=13 tr (or rr)= 16, pr=13 tr (or rr)= 8 , pr=13 tr (or rr)= 4 , pr=13 tr (or rr)= 16, pr= 3 tr (or rr)= 2 , pr=13 tr (or rr)= 1 , pr=13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz ~0.79% extended mode etpr (or erp r) = 35, tr (or rr)= 1 , pr=1 14400 ~14285.71 1 st72324jx st72324kx 105/164 seria l commun ica t ion in te rface ( c ont ?d) table 22 . sci regist er ma p and res e t value s addr ess (hex.) register label 765 43210 0050h scisr res et v alue tdre 1 tc 1 r drf 0 idle 0 or 0 nf 0 fe 0 pe 0 0051h scidr res et v alue ms b xxx xxxx lsb x 0052h scibr r res et v alue scp1 0 scp 0 0 sct2 0 sc t 1 0 sct0 0 scr2 0 s cr1 0 scr0 0 0053h scicr 1 res et v alue r8 x t8 0 scid 0 m 0 w ake 0 pce 0 ps 0 pie 0 0054h scicr 2 res et v alue tie 0 tc ie 0 rie 0 ili e 0 te 0 re 0 rwu 0 sb k 0 0055h scier p r res et v alue ms b 0 00 0000 lsb 0 0057h scipe t pr res et v alue ms b 0 00 0000 lsb 0 1 st72324jx st72324kx 106/164 10.6 10-bit a / d converter (a dc) 10.6.1 int r oduc tion the o n - c h i p ana l og t o digit al conver t e r ( a dc) pe- rip her al is a 10 -b it, su ccessive app ro xima ti on con- ve rt er wit h in te rn al samp le an d hol d cir c uit r y. this per iph e ra l ha s up t o 16 m u lt iplexe d an alo g inp u t ch ann els (r ef er t o de vice p i n o u t descrip tio n ) th at allow t h e per iph e ra l t o conver t th e an alo g volt age levels f r om up t o 16 d i ff e r en t sou r ces. the re su lt o f th e con v e r sion is st or ed in a 1 0 - b it da ta regist er . the a/d con v e r t e r is cont r o lled t h r o u g h a co nt ro l/sta t u s re gist er . 10. 6. 2 ma in fe at ures 10 -b it co nve r sio n up t o 16 cha nne ls with multiplex e d input l i ne ar successive ap pr oximat ion dat a r egist er ( d r) wh ich con t a i ns th e re su lts con v ersion co mple te st at us f l ag o n / o f f b i t ( t o r edu ce co nsump t io n) the block diagram is shown in figure 57 . figure 57. adc block diagram ch 2 c h1 e o c s p eed ad on 0 ch0 adccsr ain0 ain1 ana l og to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 4 div 4 f adc f cpu d1 d0 adcdrl 0 1 00 0000 ch3 div 2 1 st72324jx st72324kx 107/164 10-bit a/d conve r ter (adc ) ( c ont ?d) 10. 6. 3 fu nct i on al des c ri pt io n the con v e r sion is m ono to nic, me anin g th at t h e r e - su lt n ever de cr ea se s if t he ana log inpu t doe s n ot and n e ver in cr ea se s if t h e ana log inp u t doe s no t. if th e inpu t volt age ( v ain ) is gr ea te r t han v aref (h igh- level volt ag e re fe re nce) t h e n t he con v e r sion res u lt is ffh in the a dcdr h register and 03h in the ad cdrl register (w ith out overflow indication). i f th e in pu t vo lta g e (v ain ) is lower than v ssa (lo w - level volt ag e r e f e r ence) t h e n t he co nver sio n r e sult in the ad cdrh and ad cdr l regis t ers is 00 00h. the a/ d con v e r t e r is line a r an d t he dig i ta l r e sult of th e conver sion is st or ed in t h e adcdrh an d ad- cdrl re gist ers. the a ccu racy of th e conver sion is describ ed in t h e electr ical charac teris t ics sect ion. r ain is th e maximu m re co mmen de d impe dan ce fo r an an alog in put sig nal. if th e imped an ce is t o o high, this will res u lt in a los s of acc u rac y due to leakag e an d sa mplin g no t be ing comp let e d in t h e a llo te d tim e . 10. 6. 3. 1 a/ d conve r te r co nfi gur ati o n the a n a l og in put po rt s m u st b e conf igu r e d as in- put , n o pull- up, no int e r r u p t . ref e r t o th e ?i /o por t s ? cha p t e r . usin g th ese pin s as an alog in put s doe s n o t af f e ct t h e abili ty of t he p o r t t o b e r ead as a logic inp u t . i n th e adcc sr r e g i st er : ? s elect th e cs[3 :0 ] b i ts t o assign th e an alog ch an nel t o co nver t. 10. 6. 3. 2 st art i n g t h e conv ers i on i n th e adcc sr r e g i st er : ? set t h e ado n bit to e nab le t he a/ d conver t e r a n d to st ar t t h e c o n ve r s i on . fr om t h is tim e o n , th e adc per f o rm s a cont in uou s conver sion of th e se lecte d chan nel. wh en a con v e r sion is co mple te : ? the eo c bit is set by h a r d ware . ? t he result is in th e adc dr r e gist er s. a re a d to th e adcd rh re se ts th e eoc b i t. to re ad t he 1 0 bit s , per f o rm t h e f o llowing ste p s: 1. pol l the eoc bit 2. read the ad cdrl register 3. rea d t he adcdrh r egi st er . th is clea rs eoc automatically. n o te : t he da ta is n o t la tche d, so bo th t h e low and th e hig h da ta r e g i st er must be r e a d bef o r e t h e next co nver sio n is com p let e , so it is r e comme nd ed to d i sa b l e int e r r u p t s wh ile re ad in g th e co nv er sio n re - su l t . to re ad on ly 8 b i ts, p e r f o rm t he f o llo win g st ep s: 1. pol l the eoc bit 2. rea d t he adcdrh r egi st er . th is clea rs eoc automatically. 10. 6. 3. 3 chan gin g t h e c onve r si on ch anne l the a ppli c a t io n can cha nge ch ann els du ring co n- ve rsion . wh en so ft ware mo dif i es t he ch[ 3 : 0 ] bit s in th e ad ccsr r e gist er , th e c u r r e n t co nv er sio n is st op ped , t he eoc b i t is clea re d, a nd t he a/d co n- ve rt er st ar ts co nvert i n g th e newly sele ct ed cha n - nel. 10. 6. 4 low po wer mo des not e : t he a/d co nver te r may b e disable d by r e - se tt ing t h e adon bit . th is f eat ur e allo ws re duced power co nsump t io n when n o conver sion is nee d- ed . 10. 6. 5 i n te rrup t s no ne. mode desc ription w a it no effect on a/d conv erter ha lt a/ d conver t e r d i sa bled . aft e r wa ke up fr om halt mode, the a/d converter requires a s t abilization ti me t sta b ( see elect r ical char act e rist ics) be fo re a c cur a t e conve r sions can be pe rf or med . 1 st72324jx st72324kx 108/164 10-bit a/d conve r ter (adc ) ( c ont ?d) 10. 6. 6 regi st er des c ri pt ion c o n t r o l/st a t us register (a dcc sr) re ad / w r i te ( e xce pt b i t 7 r ead o nly) rese t v a lue : 00 00 00 00 ( 00h ) bi t 7 = eoc en d of conver sion this bit is set b y ha rd wa re . i t is cle a re d by har d- w a re w h en s o ftware reads the ad cdrh regis t er or writ es t o any bit o f t h e adccsr r e g i st er . 0: con v e r sion is no t comp let e 1 : co nv er sio n com p le te bi t 6 = speed adc clock selec t ion this bit is se t an d clear ed b y sof t war e . 0: f adc = f cp u /4 1: f adc = f cp u /2 bi t 5 = adon a/d converter on this bit is se t an d clear ed b y sof t war e . 0: disabl e adc and st op conve r sion 1: en able adc a nd sta r t co nver sio n bi t 4 = reserved. must b e ke pt clea re d. bit 3: 0 = ch[3:0] ch ann el select ion these bit s ar e se t and clea red b y so ft war e . th ey se lect t he an alo g inpu t t o co nver t. *the number of channe ls is de vic e dependent. refe r to the device pinout desc r iption. d a t a register (a dcd rh) re ad on ly re se t v a lue : 00 00 0 000 ( 0 0 h ) bit 7: 0 = d[ 9: 2] msb of co nv er te d ana l o g valu e d a t a register (a dcd rl) re ad on ly re se t v a lue : 00 00 0 000 ( 0 0 h ) bit 7: 2 = reser ved. for c e d by har dwar e t o 0. bit 1: 0 = d[ 1: 0] lsb of con vert e d an alog va lue 70 e o c s p eed a don 0 c h 3 ch2 ch1 c h 0 channel pin* ch3 ch2 ch1 ch0 ain0 0 0 0 0 ain1 0 0 0 1 ain2 0 0 1 0 ain3 0 0 1 1 ain4 0 1 0 0 ain5 0 1 0 1 ain6 0 1 1 0 ain7 0 1 1 1 ain8 1 0 0 0 ain9 1 0 0 1 ain10 1 0 1 0 ain11 1 0 1 1 ain12 1 1 0 0 ain13 1 1 0 1 ain14 1 1 1 0 ain15 1 1 1 1 70 d9 d8 d 7 d6 d5 d4 d 3 d2 70 0 000 00 d 1 d 0 1 st72324jx st72324kx 109/164 10-bit a/d conve r ter (con t?d ) tabl e 23 . adc regi st er ma p and rese t val u es addr ess (hex.) register label 76543 210 0070h a dccsr re s e t v a lu e eo c 0 speed 0 ad o n 00 ch3 0 ch 2 0 ch1 0 ch0 0 0071h a dcdrh re s e t v a lu e d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0072h a dcdrl r e s e t v a l u e 00000 0 d1 0 d0 0 1 st72324jx st72324kx 110/164 11 instruction set 11.1 cpu ad dress ing modes the cpu fe at ur es 17 dif f e r ent a ddr essing mod e s wh ich ca n be classif i ed in 7 main g r ou ps: the cpu i n str u ct ion set is de sig ned t o min i mize th e nu mber of b y te s r equ ire d per instr u ct ion: to do s o , mo st o f th e ad dr e ssin g m o de s m a y be su bd i- vid ed in t w o su b-m ode s calle d long a nd sho r t : ? lo ng ad dr essin g mod e is mo re p o wer f u l b e - ca use it can use t h e fu ll 64 kbyte ad dre s s spa c e, h o wever it uses mor e byt e s a nd mo re cpu cy- cles . ? sh ort a ddr essing mode is less po we rf ul b e cause i t can ge ner ally only access pa ge zer o (0 000 h - 0 0 ff h ra nge ), but th e instr u ct ion size is mo re com p a c t, an d fa st er . all m e m o ry to m e m o ry in - str u c t io ns us e sh or t a d d r e s s in g mo d e s o n ly (clr, cpl, neg, bs et, br es, b t jt, btjf, inc, dec , r l c , r rc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 24 . cpu addre s s i ng m ode ov erv i e w addressing m ode example inherent nop im mediate l d a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operatio n b set byte,#5 mode syntax destination pointer addr ess (hex.) pointer size (hex.) length (bytes) inherent nop + 0 im mediate l d a,#$55 + 1 short d irect l d a,$10 00..ff + 1 long d i rect ld a,$1000 0000..ffff + 2 no o f fset d i rect indexed ld a,(x) 00..ff + 0 short d irect i ndexed ld a,($10,x) 00..1fe + 1 long d i rect indexed ld a,($1000,x) 0000..ffff + 2 short i ndirec t ld a,[$10] 00..ff 00..ff b yte + 2 long indirec t ld a,[$10.w] 0000..ffff 00..ff w ord + 2 short i ndirec t indexed ld a,([ $10],x) 00..1fe 00..ff b yte + 2 long indirec t indexed ld a,([$10. w],x) 0000..ffff 00..ff word + 2 relative d i r ect jrne loo p pc +/ -12 7 + 1 relative indirec t jrne [$10] pc +/-12 7 00..ff b yte + 2 bit d irect b set $10,#7 00..ff + 1 bit i ndirec t bset [$10],# 7 00..ff 00..ff b yte + 2 bit d irect r elativ e b tjt $10,#7,s k ip 00..ff + 2 bit i ndirec t r e lativ e btjt [$10] ,#7,s k ip 00..ff 00..ff b yte + 3 1 st72324jx st72324kx 111/164 instru ction set over view (c on t?d ) 11. 1. 1 i nhe rent a l l inherent instructions consist o f a sing le byt e . the opcode fully specifies all t h e re quir e d inf o r m a- tio n fo r t he cpu t o pr ocess t h e o per at ion . 11. 1. 2 i mmedi at e im media t e inst ru ct ion s h a ve t w o b y t e s, th e f i rst byte cont ain s th e o p cod e , th e se co nd byte con- t a in s th e o p e r a nd va lu e. 11. 1. 3 dir ect in direct inst ru ct ion s , t h e op er and s ar e r e f e r enced by t h e i r mem o r y ad dr ess. the d i re ct a ddr essing m ode co nsist s of t w o su b- mode s: d i re ct (s h o r t) the a ddr ess is a byte , t hus re quir e s only on e byte af te r th e opco de, but only allows 0 0 - ff ad dre s s- ing space. direc t ( l on g) the ad dr ess is a wo rd, th us allowing 6 4 kbyte a d - d r es sing s p a c e , bu t r e qu ire s 2 b y t e s a fte r th e op - co de. 11.1.4 index e d ( n o off set , shor t, long) in t h is mo de, th e op er and is r e f e re nced b y it s memo ry add re ss, wh ich is d e f i ned by th e un sig ned add itio n o f a n in dex r egist er (x o r y) with an of fset . the ind i re ct add re ssing mo de consist s of t h r e e su b-m ode s: ind exe d (no of fse t ) ther e is no o f fset , (no extr a b y t e a f t e r th e op co de) , and a llows 00 - ff ad dre s sin g sp ace. ind exe d (shor t) the of fset is a byte , t h us re quir e s on ly one byt e af - te r th e op co de a nd allo ws 00 - 1 f e add re ssing sp ace. ind exe d (long) the of fset is a wor d , t hus a llowing 64 kb yt e a d - dre s sin g sp ace an d req u ir es 2 byte s af t e r t h e o p - co de. 11.1.5 indirec t (sho rt, long ) the r e q u ire d da t a byt e to do t h e ope ra tio n is fo und by it s me mor y ad dr ess, locat ed in me mor y (p oint - er) . the po int e r a d d r ess f o l l ows t he op co de . the in di- r e ct ad dr e ssin g m o d e co ns ists o f tw o su b- m o d e s : ind i rect (sho rt) th e p o in te r ad dr e ss is a b y te , th e po in te r s i ze is a byte , t hus allowin g 00 - ff ad dr essin g space, and req u ir es 1 b y te a f t e r th e opcod e. indire ct ( l on g) th e p o in te r ad dr e ss is a b y te , th e po in te r s i ze is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instr u ction function nop n o op eration trap s/w interrupt wfi wait for i n ter r u p t (low pow- er mode) halt halt oscillator (lowest power mode) ret sub-routine return ir et interrupt sub-routine return sim s et interrupt mask (level 3) rim r eset interrupt m a s k (level 0) scf s et carry flag rcf reset carry flag rsp r eset stack pointer ld load clr c lear push/pop push/pop to/from the stack in c/dec i ncrement/decrem ent tnz t est negativ e or zero cpl, neg 1 or 2 comple m ent mul b yte multiplication sll, srl, sra , rlc, rrc shift and rotate operations sw ap swap nibbles immediate instruction function ld load cp com p are bcp bit compare and, o r , xor logical operations adc, ad d, sub, sbc arithmetic operations 1 st72324jx st72324kx 112/164 instru ction set over view (c on t?d ) 11.1.6 indirec t index e d ( s h o rt , long ) this is a com b ina t io n of in dir e ct a nd sh ort in dexed add re ssing mod e s. th e op er and is r e f e r enced by its me mor y a ddr ess, which is de fin ed b y t h e un- sig ned a ddit i on o f an in dex re giste r va lue ( x or y) w i th a po in te r v a lu e loc a t e d in m e m o ry . t h e po int - er a ddr ess f o llo ws th e op co de. the ind i re ct inde xe d add re ssing mo de consist s of two sub- mo des: in dir ect ind exe d (shor t) th e po in te r a d d r e ss is a b y te , th e po in ter s i ze is a byte , t h u s a llowing 0 0 - 1 fe add re ssing sp ace, a n d re qu ire s 1 by te a fte r th e op co de . in dir ect ind exe d (lon g) th e po in te r a d d r e ss is a b yte , th e po in ter s i ze is a wo rd , th us al lowing 64 kbyte a ddr essing sp ace, a n d re qu ire s 1 by te a fte r th e op co de . table 25 . inst ruc t ions supp ort i ng direc t , in dexe d, indirec t a nd indirec t ind exe d ad dres sing mode s 11. 1. 7 rel a t i v e mode ( d i r e c t, indi rect ) this a ddr essing mod e is used t o m odif y t h e pc r e gis t er va lue , b y ad d i ng an 8- bit s i gn e d o ffs et t o it. the r e lat i ve add re ssing mo de con s ist s of t w o su b- mode s: r e l a t i v e (d irec t) the offset is following the opcode. re la ti ve ( i n d i r ect ) the o f f set is de fin e d in memo ry, which a ddr ess fo llows t he op code . long and shor t instructions fu nction ld load cp compare and, o r , xor logical operations adc, ad d, sub, sbc arithm etic additions/sub- strac t ions operations bcp b it com pare short instr u ctions only function clr c lear in c, dec i nc rement/decrement tnz t est negative or zero cpl, neg 1 or 2 complement bset, br es bit operations btjt, btjf bit tes t and jump o pera- tions sll, srl, sra , rlc, rrc shift and r o tate opera- tions sw ap swap nibbles call, jp call or jump subroutine available relative d i rect/indir ect instructions function jrxx conditional jump callr call r e lativ e 1 st72324jx st72324kx 113/164 instru ction set over view (c on t?d ) 1 1 . 2 in str uctio n gr ou ps the st 7 f a m ily de vices use an i n str u ct ion set co nsist i n g o f 63 in st r u ctio ns. th e instr u ct ions may be subdivided into 13 ma in groups as illus t rated in th e fo llowing t a b l e: us in g a pre- byt e the instr u ct ions a r e describ ed wit h o ne t o fo ur op- co des. in o r de r to e x t e n d th e n u mb er of availab l e op- co des f o r an 8-b i t cpu ( 256 opcod es), th re e dif f e r - ent pr eb yt e o p code s a r e def ine d . the s e pr ebyt e s mod i fy t he me anin g of t he in st r u ctio n t hey pr e- ce de. t h e wh ole in st ru ctio n be co m e s : pc-2 en d o f pr ev iou s ins t ru ct ion pc-1 prebyte pc o p code pc+1 additional w o rd (0 to 2) according to t h e num ber of b y t e s re quir e d t o com put e t he e f - fe ct ive ad dre s s these pr eb yt es ena ble inst ru ct ion in y a s well as indir e ct a ddr essing m ode s t o be imple m en te d. they pr eced e th e opcod e of th e instr u ct ion in x or th e in st r u ctio n using dir e ct ad dre s sin g m ode . the pre b yt es a r e: pdy 90 rep l ace a n x based inst ru ct ion using im med i at e, dir e ct, ind e xed , o r in her en t a d - d r es sing m o de b y a y o n e . pi x 9 2 rep l ace an instr u ct ion usin g di- rect , d i re ct bit , or dir e ct r e la tive a ddr essing m ode to an instr u ct ion using th e cor r e s p ond ing indir e ct add re ssing m ode . it also ch ang es an inst ru ct ion u s in g x in dexed a d - dre s sin g m ode t o an in st ru ctio n u s ing ind i rect x in- dexed a ddr essing mo de. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer l d clr sta ck operation p us h p op rsp increment/decrem e n t inc dec compare and tes t s c p t n z bcp logical operations and o r x or c p l n eg bit o peration bse t bres conditional bit test and branch b tjt b tj f arithm etic operations adc a dd sub s bc mul shift and rotates sll srl sra r l c rrc s w ap sla unconditional j u m p or call jra j rt jrf j p c all c allr nop r et conditional branch j rxx interruption management trap wfi h alt i ret condition code flag modification sim r im scf r cf 1 st72324jx st72324kx 114/164 instru ction set over view (c on t?d ) mnemo d escription function/example d st src i 1 h i0 n z c adc a dd with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp b it c o mpar e a, m e m o ry t s t (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf j u mp if b i t i s fal s e (0) b tj f byte , #3, jmp1 m c btjt j u mp if b i t i s tr ue ( 1 ) b tj t byte , #3, jmp1 m c call call subroutine callr call subroutine relative clr c lear reg, m 0 1 cp arithmetic c o mpare t st(reg - m) reg m n z c cpl o ne c o mplement a = ffh -a reg, m n z 1 dec d ecrement dec y r eg, m n z halt halt 1 0 ir et interrupt routine return pop cc, a, x, pc i1 h i 0 n z c in c i ncrem ent inc x r eg, m n z j p abs o lute j u mp j p [ t bl.w] jra j um p relative alw a ys jrt j um p relative jrf n ever jump jrf * jrih j u m p if e x t. int pin = 1 ( ext. int pin high) jril j u m p if e x t. int pin = 0 ( ext. int pin low) jrh j um p if h = 1 h = 1? jrnh j u m p if h = 0 h = 0? jrm j um p if i1:0 = 11 i1:0 = 11? j rnm jum p i f i1:0 <> 11 i 1 :0 <> 11? jrmi j u m p if n = 1 (minus) n = 1? jrpl j u mp if n = 0 (plus) n = 0? jreq j u m p if z = 1 (equal) z = 1? jrne j u m p if z = 0 (not equal) z = 0? jrc j um p if c = 1 c = 1? jrnc j u m p if c = 0 c = 0? jrult j um p if c = 1 u nsigne d < jruge j um p if c = 0 j mp if unsigned >= jrugt j um p if (c + z = 0) unsigne d > 1 st72324jx st72324kx 115/164 instru ction set over view (c on t?d ) mnemo d escription function/example d st sr c i 1 h i0 n z c jrule j um p if (c + z = 1) unsigne d <= ld load dst <= s r c r eg, m m , reg n z mul m ul ti pl y x ,a = x * a a , x, y x , y, a 0 0 neg n egate (2's compl) neg $10 reg, m n z c nop n o o peration or or operation a = a + m a m n z pop p op from the sta c k pop reg r eg m pop cc c c m i 1 h i0 n z c push push onto the stack push y m reg, cc rcf reset c a rry flag c = 0 0 ret s ubroutine r e turn rim enable interrupts i 1:0 = 10 (le v el 0) 1 0 rlc r otate le ft true c c <= a <= c r eg, m n z c rrc rotate right true c c => a => c r eg, m n z c rsp r eset stack pointer s = m a x allowed sbc substrac t with carry a = a - m - c a m n z c scf s et carry flag c = 1 1 sim d isable interrupts i 1:0 = 11 (le v el 3) 1 1 sla shift left arithmetic c <= a <= 0 r eg, m n z c sll shift left logic c <= a <= 0 r eg, m n z c srl shift right logic 0 => a => c r eg, m 0 z c sra s hift right arithmetic a7 => a => c r eg, m n z c sub s ubstrac tion a = a - m a m n z c sw ap swap nibbles a7-a4 <=> a3-a0 r eg, m n z tnz t es t for neg & zer o tnz l b l 1 n z trap s/w trap s/w interrupt 1 1 wfi w ai t for i n ter r upt 1 0 xor e xc lusive or a = a xor m a m n z 1 st72324jx st72324kx 116/164 12 elect r ical characterist i cs 12. 1 p a ra me te r co nd i t i o n s un less ot he rwise spe c if ie d, all vo lt age s ar e r e - fe rr ed t o v ss . 12. 1. 1 mi ni mum and ma xi mu m v a l u es un less o t h e rwise specif ied t h e min i mum a nd ma x- imum valu es a r e gua ran t eed in th e wo rst co ndi- tio n s of a m bie n t t e mp er at ure , su pp ly vo lta ge and fr eq uen cie s by t e sts in pr odu ct ion on 10 0% o f t h e devices with an am bien t te mpe r a t u r e at t a =25c and t a =t a m a x ( g iven by t h e sele ct ed t e mp er at ure ra nge ). da ta b a sed on cha r a c t e r i zat i on r e sult s, design sim u lat i on an d/ or te ch nolo g y char act e r i st ics are indicat e d in th e t a b l e f o o t n o t e s a nd are no t te st ed in pr od uctio n . based on cha r a c t e r i zat i on, t h e min- imum and ma xim u m va lues r e f e r t o sam p le te st s and r e p r ese n t t h e me an valu e plus or min u s th ree tim e s t h e st and ar d devia tio n (me an3 ). 12. 1. 2 ty pi cal val ue s un less o t h e rwise specif ied, typ i ca l d a t a ar e based on t a =25c, v dd =5 v. th ey a r e g i ve n only as de- sig n guid e lin es a nd ar e no t t e st ed . 12. 1. 3 ty pi cal curv es un less ot he rwise sp ecifie d, a ll t y pical cu rves are given o n ly a s d e sign g u ide lines an d ar e no t t e ste d . 12. 1. 4 lo adi ng ca paci t o r the lo adin g cond itio ns used f o r pin pa ra met e r mea s u r e m ent ar e sh own in f i gu r e 58 . figure 5 8 . pin lo ading con d itions 12. 1. 5 pi n i n p u t vol t age the in put volt age mea s u r em ent on a pin o f t h e d e - v i ce is desc ribed in figu re 5 9 . fig u re 59 . pi n inp u t vo lt age c l st7 p in v in st7 p in 1 st72324jx st72324kx 117/164 12. 2 abso lute m a xi mum rati ngs st r e sse s abo ve th ose list ed a s ? a b s o l ut e ma xi- mum ra tin g s? m a y cause per man e n t d a ma ge to th e d e vice . t h is is a st ress ra t i ng o n ly an d f u n c - tio nal op er at ion of t h e d e vice un de r th ese co ndi- tio n s is no t implie d. exposur e to ma ximu m r a t i ng co ndit i on s f o r ext e n ded p e rio d s m a y a f f e ct d e vice reliability. 12. 2. 1 vol t a g e chara c t e ri st ic s 12. 2. 2 curre nt char act eri s t i cs n o tes: 1. directly connecting the reset an d i/o pins to v dd or v ss could dam age the dev ic e if an uni ntentional internal reset is generated or an unexpected change of the i/o configuration occurs (for ex am pl e, due to a corrupt ed program c ounter). to guarantee safe operation, this c onnection has to be done through a pull-up or pull-down resistor (typical: 4.7k ? for reset , 10k ? for i/o s ). for the same reason , unused i/ o pins must not be directly tied to v dd or v ss . 2. i inj( p i n) m ust nev er be exc eeded. this is implicitly ins ured if v in maximum is re specte d. if v in maximum c annot be respected, the injection current m u s t be limited externa l ly to the i inj( pi n) v a lue. a positive injection is induced by v in >v dd w h ile a negative injection is induced by v in st72324jx st72324kx 119/164 oper ating c o nd itio ns ( c ont ?d) 12.4 lvd/a vd char acter istics 12.4.1 opera t ing condi tions with low volt age det e c t or ( l vd) su bje c t to g ene ra l o per at ing co ndit i on s f o r t a no te s : 1. data based on characterization results, not te sted in production. 2. if the medium or low thresholds are selected, the detec tion may occur out side the spe c ified oper ating voltage range. 12. 4. 2 auxi l i a r y vol t a ge dete ct or (avd) thre s ho lds su bje c t to g ene ra l o per at ing co ndit i on s f o r t a 1. data based on characterization results not tested in p r oductio n . symbo l parameter c onditions m i n t yp ma x u n i t v it+( lv d) res et release threshold (v dd ri se) vd level = h i gh in option byte 4 . 0 1) 4.2 4.5 v vd lev e l = med. in option by te 2) 3.55 1) 3.75 4.0 1) vd level = low in option byte 2) 2.95 1) 3.15 3.3 5 1) v it- ( l v d) res et generation threshold (v dd fal l ) vd level = h i gh in option byte 3.8 4 .0 4.25 1) vd lev el = med. in option by te 2) 3.35 1) 3.55 3.7 5 1) vd level = low in option byte 2) 2.8 1) 3.0 3 .15 1) v hys ( l v d ) lvd voltage threshold hys t eresis 1) v it +(l v d) -v it -( lvd) 150 200 250 mv vt po r v dd ri se ti me 1) 6 s/ v 100ms/v t g( vdd) filtered glitch delay on v dd 1) not detected by the lvd 4 0 n s symbo l parameter c onditions min t yp max u nit v it+( av d) 1 ? 0 avdf flag toggle threshold (v dd rise ) vd level = h i gh in option byte 4.4 1) 4.6 4 .9 v vd level = m ed. in option by te vd level = low in option byte 3.95 1) 3.4 1) 4.15 3.6 4.4 1) 3.8 1) v i t -( avd) 0 ? 1 avdf flag toggle threshold (v dd fal l ) vd level = h i gh in option byte 4.2 4 .4 4.65 1) vd level = m ed. in option by te vd level = low in option byte 3.75 1) 3.2 1) 4.0 3.4 4.2 1) 3.6 1) v h y s( avd) avd voltage threshold hysteresis v it +(a v d) -v it - ( av d) 200 m v ? v it- voltage drop between avd flag set and lvd reset activated v it-( avd) -v i t -(lv d ) 450 mv 1 st72324jx st72324kx 120/164 12.5 supp ly cur rent char acter istics the f o llo win g cu rr ent co nsump t io n sp ecifie d fo r th e st 7 fu nctio nal op er at ing mod e s o v e r t e mp era t u r e ra nge doe s n o t t a ke int o acco unt t h e clo c k sou r ce cur r e n t co nsump t io n. to get t he t o t a l device con s u m p- tio n , t h e two cur r en t valu es mu st be a dde d (e xcep t f o r halt mo de f o r wh ich t h e clock i s sto ppe d) . 12.5.1 cur rent consumption n o tes: 1. data based on characterization results, tes t ed in prod uction a t v dd max. and f cpu ma x. 2. m eas urements are done in the following cond itions : - program e x ecuted from ram , cp u running with ram ac cess. the increase in consumption when executing from flas h is 50%. - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in res e t state. - lvd disabled. - clock input (osc1) driven by external square wave . - in slo w and slow w a it mode, f cp u is based on f osc divided by 32. to obtain the to tal current consumption of the device, add the clock s ource ( section 12.6.3 ) an d the peripheral power c onsumption ( section 12.5.3 ). 3. all i/o pins in push-pull 0 m o de (when app licable) with a s t atic value at v dd or v ss (no load), lvd di sabled. data bas ed on charac teriza tion results, tested in production at v dd max. and f cp u max. 4. data bas ed on characterisation results , not tested in production. all i/o p i ns in push-pull 0 mode (when applica b le) w i th a static value at v dd or v ss (no load); clock input (o sc1) driven by ex ternal square wave, l v d disabled. to obtain the total current consumption of the dev ice, add the clock source consumption ( section 12.6.3 ). symbol par a meter c onditio ns flash device s unit typ max 1) i dd supply current in ru n m o d e 2) f os c =2mhz, f cp u =1m h z f os c =4mhz, f cp u =2m h z f os c =8mhz, f cp u =4m h z f os c =16mhz, f cp u =8mh z 1.3 2.0 3.6 7.1 3.0 5.0 8.0 15.0 ma supply current in slo w mode 2) f os c =2mhz, f cp u =62.5k h z f os c =4mhz, f cp u =125khz f os c =8mhz, f cp u =250khz f os c =16mhz, f cp u =500khz 600 700 800 1100 2700 3000 3600 4000 a supply current in w ait mode 2) f os c =2mhz, f cp u =1m h z f os c =4mhz, f cp u =2m h z f os c =8mhz, f cp u =4m h z f os c =16mhz, f cp u =8mh z 1.0 1.5 2.5 4.5 3.0 4.0 5.0 7.0 ma supply current in slo w wait m o d e 2) f os c =2mhz, f cp u =62.5k h z f os c =4mhz, f cp u =125khz f os c =8mhz, f cp u =250khz f os c =16mhz, f cp u =500khz 580 650 770 1050 1200 1300 1800 2000 a supply current in ha lt mode 3) -40c t a +85c < 1 1 0 a -40c t a +125c < 1 5 0 i dd supply current in ac tive-halt mode 4) f os c =2mhz f os c =4mhz f os c =8mhz f os c =16mh z 80 160 325 650 no m a x . guaran- teed 1 st72324jx st72324kx 121/164 s u pply c urre nt ch ara cteristics (con t?d ) 12. 5. 1. 1 pow e r consu m p t i on vs f cpu : f la s h de vi ce s figure 6 1 . ty pical i dd in run mode figure 6 2 . ty pical i dd i n slow mode fig u re 63 . ty pical i dd in wait mode fig u re 64 . ty p. i dd in slo w - w ait mode 0 1 2 3 4 5 6 7 8 9 4 4 .4 4 .8 5 .2 5 .5 v dd ( v ) idd (ma) 8m h z 4mhz 2mhz 1mhz 0.0 0 0.2 0 0.4 0 0.6 0 0.8 0 1.0 0 1.2 0 4 4. 4 4. 8 5. 2 5. 5 vd d ( v ) idd (ma) 500khz 2 50k h z 125khz 62 . 5k h z 0 1 2 3 4 5 6 4 4 .4 4.8 5 .2 5 . 5 vd d ( v ) idd (ma) 8m h z 4mhz 2mhz 1mhz 0.0 0 0.2 0 0.40 0.6 0 0.8 0 1.0 0 1.2 0 4 4 .4 4.8 5 .2 5.5 vd d ( v ) idd (ma) 500khz 250 k h z 125 k h z 62. 5khz 1 st72324jx st72324kx 122/164 supply c urre nt ch ara cteristics (con t?d ) 12.5.2 supp ly a nd cloc k man a ger s the pre v io us curr en t con s u m pt ion specif ied f o r t he st7 fu nct i ona l ope ra tin g mo des over t e mp era t u r e ra nge doe s n o t t a ke int o acco unt t h e clo c k sou r ce cur r e n t co nsump t io n. to get t he t o t a l device con s u m p- tio n , t h e two cur r en t valu es mu st be a dde d (e xcep t f o r halt mo de ). no te s : 1. data based on characterization res ults done with the external c om pone nts specified in section 12.6.3 , not tested in production. 2. as the os cillator is based on a current sour ce, the cons um ptio n does not depend on the vo ltage. symbol par ameter c onditions typ m ax unit i dd(rcint) s upply current of inte rnal rc os cillator 625 a i dd(re s) s upply current of re sonator oscillator 1) & 2) see sec t ion 12.6.3 on page 125 i dd(p ll) p ll supply current v dd = 5v 360 a i dd(lv d) lv d supply c u rrent v dd = 5v 150 300 1 st72324jx st72324kx 123/164 s u pply c urre nt ch ara cteristics (con t?d ) 12. 5. 3 o n-chi p peri phe ral s t a = 25 c f cpu =4mhz. n o tes: 1. data based on a d i fferential i dd measurement between res e t configur ation (timer count er running at f cpu /4) and timer counter stopped (only ti md bit set). data valid for o ne timer. 2. data based on a differential i dd measurement between reset configu r ation (spi disabled) and a perm a nent spi m a s t er communic a tion at m a x i mum speed (data s ent equal to 55h) . this measurem ent includes the pad toggling consump- tion. 3. data based on a differential i dd m eas urement between sci low power sta t e (sc i d=1) and a permanent sci data trans- mit sequence. 4. data based on a differential i dd measurement between reset c onfigur ation and continuous a/d conversions. symbol parameter c onditions typ u nit i dd(tim) 16-bit timer supply current 1) v dd = 5.0v 50 a i dd(s p i) spi supply current 2) v dd = 5.0v 400 i dd( sci) sci supply current 3) v dd = 5.0v 400 i dd(a dc) adc supp ly current when converting 4) v dd = 5.0v 400 1 st72324jx st72324kx 124/164 12.6 clock and timing c hara cteristics su bje c t to g ene ra l o per at ing co ndit i on s f o r v dd , f cpu , an d t a . 12. 6. 1 g e ner a l t i mi ngs 12. 6. 2 ext e rn al cl ock sou r ce figure 6 5 . ty pical ap plic ation wit h an ext e rna l clock sour ce n o tes: 1. data based on typic a l applica t ion softw are. 2. time m eas ured between interrupt event and interrup t vecto r fetch. ? t c(ins t ) is the num ber of t cpu cycles needed to finis h the current instru ction execution. 3. data based on design simulation and/or technol ogy characteristics, not tested in production. symbo l parameter conditions m i n t yp 1) max u nit t c(ins t ) i n st ruct ion cy cle time 23 1 2 t cpu f cp u =8m h z 250 375 1500 ns t v(it) inte rrupt reaction time 2) t v(it) = ? t c(ins t ) + 10 10 22 t cpu f cp u =8mhz 1 .25 2 .75 s symbo l parameter c onditions min t yp max u nit v os c1h osc1 input pin high lev e l voltage see figure 65 v dd -1 v dd v v os c1 l osc1 input pin low level voltage v ss v ss +1 t w(osc1h) t w( osc1 l) osc1 high or low time 3) 5 ns t r( o s c 1 ) t f( os c1 ) osc1 r i se or f a l l ti me 3) 15 i l osc1 input leakage current v ss v in v dd 1 a osc1 osc2 f osc ex ter nal st72xxx cl ock s ource not connected internally v osc1l v os c1h t r(osc 1) t f(osc1 ) t w( o s c1 h) t w( o s c 1 l ) i l 90 % 10% 1 st72324jx st72324kx 125/164 c l ock an d timin g cha racter istic s (c on t?d ) 12. 6. 3 crys ta l an d cer a mi c re sona to r o s c i l l a to rs the st7 int e r nal clock ca n be su pp lied wit h f our different crystal/ceramic res o nator os cillators. all th e inf o r m at ion g i ve n in t h is p a r agr ap h ar e based on ch ara c te rizat i on re su lts wit h spe c if ied t y p i ca l exte rn al comp one nt s. i n t h e app lica t io n, t he r e so- nat or an d th e loa d capa cit o r s have t o be place d as c l os e as poss i b le to the osc illator pins i n order to minimize output distorti on and start-up stabiliza- t i on tim e . re fe r to th e cr yst al/ c e r a m ic re so na to r manu f a ctu r er f o r mo re det ails ( f r e q uen cy, pa ck- age, accuracy ... ). fi gure 6 6. ty pi cal ap pl ic ati o n w i t h a cr yst al or ce rami c reso nat o r n o tes: 1. the oscillator selection c an be opt im ized in term s of supply current us i ng an high quality resonat or with small r s value. r e fer to crystal/ceram ic reso nator manufac turer for more details . 2. data based on characterisation results, not te sted in production. symbol parame ter c onditions min m ax unit f os c o s c i llator frequency 1) lp: low power oscillator mp: medium power oscillator ms: medium speed o scillator hs: high spe ed osc i llator 1 >2 >4 >8 2 4 8 16 mhz r f feedback resisto r 2) 20 40 k ? c l1 c l2 r e c o m m ended load capac itance v e r- sus equiva lent serial res i stance of the crys tal or c e ramic resonator (r s ) r s =200 ? lp osc i llator r s =200 ? m p oscillator r s =200 ? m s oscillator r s =100 ? hs oscillator 22 22 18 15 56 46 33 33 pf symbol parame ter c onditions typ m ax unit i 2 o sc2 driving curren t v in =v ss lp osc i llator m p oscillator m s oscillator hs oscillator 80 160 310 610 150 250 460 910 a osc 2 osc1 f os c c l1 c l2 i 2 r f st72xxx re sona tor when res onat o r w ith inte gra ted ca pac it ors 1 st72324jx st72324kx 126/164 c l ock an d timin g cha racter istic s (c on t?d ) n o tes: 1. resonator c haracteristic s given by the ceramic resonator manufacturer. 2. t su(o sc) is the typical oscillator start-up time measured b e tween v dd =2.8v and the fetch of the first instruction (with a quic k v dd ramp-up from 0 to 5v (<50 s) . 3. r e s onators all have different characte ristics. contact the m anufacturer to obt ain the appropriate va lues of external components and to verify osc i llator performance. 4. 3rd overtone resonators r equire specific validation by the resonator manufacturer. o scil. typical ceramic resonator s (information for guidanc e only) c l1 [pf] c l2 [pf] t su(osc) [ms] 2) reference 3) freq. c haracteristic 1) ceramic lp murata c sa2.00m g 2mhz ? f osc =[0.5% t o ler ance ,0.3% ? ta , 0.3% agin g , x .x% corre l ]2 2 2 2 4 mp c sa4.00m g 4mhz ? f osc =[0.5% t o ler ance ,0.3% ? ta , 0.3% agin g , x .x% corre l ]2 2 2 2 2 ms c sa8.00m t z 8mhz ? f osc =[0.5% t o ler ance ,0.5% ? ta , 0.3% agin g , x .x% corre l ]3 3 3 3 1 hs c sa16.00mx z 040 4) 16mhz ? f osc =[0.5% t o ler ance ,0.3% ? ta , 0.3% agin g , x .x% corre l ]3 3 3 3 0 . 7 1 st72324jx st72324kx 127/164 clock ch arac teristics (con t?d ) 12. 6. 4 rc o sci l l a t or s figure 6 7 . ty pical f osc( rcint ) vs t a not e : to reduce disturbanc e to the rc os cillator, it is re co mme nde d t o pla c e deco uplin g capa cit o r s between v dd and v ss as shown in figure 86 symbol para meter c onditions min t yp max u nit f osc (rcint) internal rc oscillator frequency s ee figure 67 t a =25c, v dd =5 v 23 . 5 5 . 6 m h z 3 3. 2 3. 4 3. 6 3. 8 4 - 45 0 25 70 13 0 t a ( c ) f osc(rci nt) (mhz) vd d = 5 v vdd = 5.5v 1 st72324jx st72324kx 128/164 clock ch arac teristics (con t?d ) 12. 6. 5 pll char act eri s t i cs no te : 1. data charac teriz ed but not tested . the user must t a ke t h e pll jitt e r in to acco un t in t he app lica t io n ( f or examp l e in se ria l commu n icat ion or sa mplin g of h i gh fr equ en cy signa ls). the pll jitt e r is a p e r i odic ef f e ct , which is in t egr at ed over se ve ra l c pu cyc les . therefore the lo nger the period of the application sign al, the less it will be impacted by the p l l jitter. figu re 6 8 shows th e pll jitt e r int e g r a t e d on app lica t io n signa ls in th e r ang e 12 5khz t o 2m hz. at f r e que n- c i es o f le ss th an 1 2 5 kh z, the j i tter is negligible. figure 6 8 . int e gra t e d pl l j i t t e r vs s i gn al f r eq uenc y 1 note 1: mea s u r e m ent cond itio ns: f cpu = 8mhz. symbol par a meter c ondition s m in typ m ax unit f os c pll input frequency ran ge 2 4 mhz ? f cpu / f cpu instanta neous pll jitter 1) flash st72f324, f os c = 4 mhz. 1.0 2 .5 % flash st72f324, f os c = 2 mhz. 2.5 4 .0 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 4 m h z 2 m h z 1 m h z 5 00 k h z 2 50 k h z 1 25 k h z a p p lic a t ion fr e que nc y + / -j itte r (% ) flash typ rom max rom typ 1 st72324jx st72324kx 129/164 12.7 memor y ch arac teristics 12. 7. 1 ram a nd hardw a re reg i s t er s 12. 7. 2 fl ash m e mory n o tes: 1. minimum v dd supply voltage w i thout losing data stored in ram (in halt mode or under re set) or in hardware reg- isters (only in halt m ode). not tes t ed in production. 2. data based on characterization results, not te sted in production. 3. v pp must be applied only during the programm i ng or erasi ng operation and not permanently for reliability reasons . 4. data based on simulation resu lts, not tested in production . symbo l parameter conditions m i n t yp max u nit v rm data retention mode 1) ha lt mode (or res et) 1.6 v dual voltag e h d flash memo ry symbol par a meter conditio n s m in 2) typ m ax 2) unit f cp u operating frequency read m ode 0 8 mhz write / eras e mode 1 8 v pp programm i ng voltage 3) 4.5v v dd 5.5v 11.4 12.6 v i dd supply c u rrent 4) write / erase 0 ma i pp v pp current 4) read (v pp =12v) 200 a write / erase 3 0 m a t vp p internal v pp stabilization time 10 s t ret data re tent ion t a =55c 20 y ears n rw write eras e cyc les t a =25c 100 cyc l es t prog t er a se programm i ng or erasing tempera- ture range -40 2 5 8 5 c 1 st72324jx st72324kx 130/164 12.8 emc c har acteristics s u sc eptibility tests are pe rformed on a sample ba- s i s d u r in g pr od u c t ch ar ac te riza tio n . 12. 8. 1 f unct i onal ems ( e le ctr o mag n et ic su sce pt ibi l i t y ) ba sed on a simp le run n in g a pplicat io n o n t h e pr odu ct (t og gling 2 leds t h r o u gh i / o por t s ) , t h e pr odu ct is st r e sse d by t w o elect r o ma gne tic event s unt il a fa ilur e occurs (in d icat ed b y t he leds). es d : electro-static dis charge (pos itive and n e g a t iv e) is ap p lied o n all pin s of th e de vic e un til a fu nctio nal d i st ur ba nce occu rs. t h is t e st co nf orm s with th e iec 100 0- 4-2 st an dar d. ftb : a bur s t of fa st tr ansien t volt ag e ( posit ive and n ega tive) is ap plied t o v dd a nd v ss th ro ugh a 10 0pf ca pacit or , u n t il a f u n c t i on al dist ur ban ce occu rs. t h is te st conf or ms wit h t h e iec 10 00- 4- 4 st an dar d. a de vice re set allo ws nor ma l op er at ions to b e r e - su med . the t e st re sult s ar e g i ve n in t h e t a b l e be- low ba se d on th e ems levels an d cla s ses d e f i ned in app lica t ion no te an17 09. 12. 8. 1. 1 des i gn in g h a rde n ed so ft war e to av oi d noise pr oblems em c char act e r i za tio n and o p t i mizat i on a r e pe r- fo rme d at co mpo nen t level wit h a typical ap plica- t i on en vir o nm e n t a n d s i mp lifie d m c u so ftw ar e. it sh ould be no te d t h a t g ood emc pe rf or man c e is high ly d epe nde nt on t he u s e r ap plicat ion a nd t h e s o ftware in partic u lar. ther ef or e it is r e com m en ded t h a t t he user app lies em c sof t war e op timiza tio n and p r eq ua lificat ion te st s in re lat i on wit h t he emc level r equ est ed f o r his a pplicat io n. so ft war e rec o mm e nda tions : the sof t war e flo w cha r t m u st includ e t h e ma nag e- ment of run a way co ndit i on s such as: ? corr up te d pr ogr am cou n t e r ? unexpe ct ed r e set ? cr itic al dat a co rr up tio n (c on tr ol re gis t e r s. ..) p r e q u a l i fi ca ti o n tria ls : most of th e commo n fa ilur e s ( u n e xpect ed r e set and pro g r a m cou n t e r cor r u p t i on ) can b e r epr o- duced b y man ually f o rcing a low st at e on th e re- s et pin or the os cillator pins for 1 second. to co m p le te th es e tr ia ls, esd str e s s ca n b e ap - plied d i rect ly on t h e d e vice , over t h e r ang e of sp ecificat ion va lue s . when une xp ect ed b eha vio u r is de t e cte d , th e sof t war e can b e ha rd ene d t o pr e- ve nt un reco ve rab l e e r r o r s occu rr ing (see ap plica- tio n not e an101 5 ) . symbol parameter c onditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance 8 or 16k flas h device, v dd = 5v, t a = +25c, f os c = 8mhz c onform s to iec 1000-4-2 4b v fftb fast transient voltage bur st limits to be applied through 100pf on v dd and v dd pins to induce a func- tional disturbance v dd = 5v , t a = +25c, f os c = 8mhz conforms to iec 1000-4-4 4a 1 st72324jx st72324kx 131/164 e m c cha rac te ristic s (con t?d ) 12. 8. 2 el ect ro ma gnet i c int e r f er enc e (emi ) ba sed on a simp le app lica t io n run n in g o n t h e pr odu ct (t og gling 2 leds t h r o u gh t h e i / o po rt s), th e p r o duct is mo nit o r ed in te rms o f emission. this emission t e st is in l i ne wit h t he n o rm sae j 175 2/ 3 wh ich spe c ifie s t he bo ar d and t h e lo adin g of each pin . n o tes: 1. data based on characterization results, not te sted in production. 2. refer to application note an1709 for data on other package types. symbol parameter c onditions device/ package monitored frequency band max vs. [f os c /f cpu ] unit 8/4mhz 16/8m hz s emi p eak level v dd = 5v, t a = +25c c onform i ng to sae j 1752/3 8/16k flash/ tqfp44 0.1mhz to 30m hz 12 18 db v 30m hz to 130mhz 19 25 130m hz to 1ghz 15 22 sa e em i lev el 3 3 .5 - 32k flas h/tqfp44 0.1mhz to 30m hz 20 21 db v 30m hz to 130mhz 26 31 130m hz to 1ghz 22 28 sa e em i lev el 3.5 4 .0 - flash/tq f p 32 0.1mhz to 30m hz 25 27 db v 30m hz to 130mhz 30 36 130m hz to 1ghz 18 23 sa e em i lev el 3.0 3 .5 - 1 st72324jx st72324kx 132/164 e m c cha rac te ristic s (con t?d ) 12. 8. 3 abso lu te ma xi mum ra ti ngs ( e le ct ric a l se nsi t iv it y) ba sed on th ree dif f e r e n t t e st s ( esd, lu and dl u) using specif ic me asur eme n t me th od s, t h e p ro duct is str e sse d in o r de r t o de te rm in e it s p e r f o r m a nc e in te rms o f elect r ical sen s itiv ity . f o r mo re d e t a ils, re - fe r t o th e app lica t ion no te an11 81. 12. 8. 3. 1 el ect ro- s ta ti c di s c har g e (esd) ele c t r o- st at ic disch ar ges (a po sit i ve th en a neg a- tive pulse sepa ra te d by 1 second ) ar e a pplie d to th e pins of each sam p le accor d ing to e a ch pin co mbin at ion. t he sa mple size de pen ds o n t h e numb e r of sup p ly pin s in t he device ( 3 p a r t s*( n +1) su pply pin) . two mod e ls can b e simu lat ed: hu man bo dy m ode l an d machin e mod e l. th is t e st co n- fo rms to t h e jesd22- a114 a/a1 15a sta nda rd . ab sol u te maxi mum rati ngs n o tes: 1. data based on characterization results, not te sted in production. 12. 8. 3. 2 st ati c a nd dy nami c lat c h- up lu : 3 c o m p lem e nt ar y st at ic te sts a r e r e q u ir e d on 10 p a rt s t o a s sess t h e la tch- up p e r f o rma nce. a sup p ly o v e r volt ag e (a pp lied t o ea ch p o wer su pply p i n) and a cu rr ent in jectio n ( app lied to each in put , ou tp ut and conf igu r a b le i / o p i n) are per fo rm ed o n ea ch sa mple . th is te st conf or ms to t he ei a/ jesd 78 i c lat ch- up st a nda rd . for mor e det ails, r e f e r t o t he ap plicat ion no te an11 81 . dlu : elect r o- st at ic dischar ge s (o ne posit ive t h e n one ne gat ive t e st ) ar e a pplie d t o ea ch pin of 3 sa mp le s wh en th e m i cr o is ru n n in g t o a s se ss th e lat ch- up p e rf or ma nce in dyna mic m ode . power supp lies ar e se t to t h e t y p i ca l values, the os cillator is connected as near as p o ssible t o th e pin s of th e micr o an d t h e com pon en t is put in re set m ode . th is t e st conforms to the iec 1 000-4-2 and saej1752/3 sta n d a r d s. fo r m o re de ta ils, r e fer to th e a p p lica t io n not e an118 1. e l ec t r i c a l sens it iv iti e s n o tes: 1. class description: a class is an stm i cr oele c tronic s internal specif icatio n. all its lim its are high er than the jedec spec- ific ations, that means when a devic e belongs to class a it exc eeds the jedec standar d. b c l ass strictly co vers all the jede c criteria (int ernational standard). symbol ratings conditions maximum value 1) unit v e s d(hb m) e l ectro-static disc harge voltage (human body m o del) t a = +25c 2000 v v es d(mm) e l ectro-static disc harge voltage (machine model) t a = +25c 20 0 v esd(cd) e l ectro-static disc harge voltage (charge d device m odel) t a = +25c 250 symbol parameter c onditions class 1) lu s t atic la tch-up c l ass t a = +25c t a = +85c t a = +125c a a a dlu d y nam ic latch-up class v dd = 5.5v , f os c = 4mh z , t a = +25c a 1 st72324jx st72324kx 133/164 12.9 i/o p o r t pin cha rac ter i stic s 12. 9. 1 g e ner a l cha r ac ter i s t i c s su bje c t to g ene ra l o per at ing co ndit i on s f o r v dd , f osc , an d t a un le ss ot he rw ise sp ec ifie d. n o tes: 1. data based on characterization results, not te sted in production. 2. hysteresis voltage between s c hm itt tr igger s w itching levels. based on c haracterization res u lts, not tested. 3. when the curren t lim itation is not poss i ble, the v in maximum m u s t be respe c ted, otherwise refer to i inj( pi n) specifica- tion. a pos itive injection is induc ed by v in >v dd while a negative injection is induced b y v in st72324jx st72324kx 135/164 i/o port pin ch ara cteristics (cont ?d ) figure 7 4 . ty pical v ol vs . v dd ( s td. ports ) figure 7 5 . ty pical v ol vs . v dd (high- sink po rts ) figure 76. typical v oh vs. v dd 0 0. 1 0. 2 0. 3 0. 4 0. 5 0. 6 0. 7 0. 8 0. 9 1 22 . 5 33 . 5 4 4 . 5 5 5 . 5 6 vd d ( v ) v o l ( v ) a t ii o = 5 m a t a=-45c t a=25c t a=95c t a=140c 0 0. 0 5 0. 1 0. 1 5 0. 2 0. 2 5 0. 3 0. 3 5 0. 4 0. 4 5 22 . 5 33 . 5 4 4 . 5 5 5 . 5 6 vdd(v) vol(v) at ii o=2m a ta=-45c ta=25c ta=95c ta=140 c 0 0. 1 0. 2 0. 3 0. 4 0. 5 0. 6 2 2 . 5 3 3 . 544 . 555 . 5 6 vd d ( v ) v o l ( v ) at i i o= 8m a ta= 140c ta=95c ta=25c ta=-45c 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 1. 4 1. 6 2 2 .5 3 3 .5 4 4 . 5 5 5 . 5 6 v dd( v ) v o l ( v ) at i i o= 2 0m a t a = 140 c t a=95c t a=25c t a=-45c 0 1 2 3 4 5 6 2 2 . 5 33 . 544 . 5 5 5 . 5 6 v dd ( v ) vdd- v oh(v) at iio=-5m a ta = - 4 5 c ta=25c ta=95c ta=140c 2 2.5 3 3. 5 4 4. 5 5 5. 5 2 2 . 5 3 3 . 5 44 . 555 . 56 v dd( v ) vd d - vo h ( v) a t i i o = - 2 m a ta = - 4 5 c ta=25c ta=95c ta=140c 1 st72324jx st72324kx 136/164 12.10 con t rol pin cha racter istic s 12.10.1 asynchronous reset pin su bje c t to g ene ra l o per at ing co ndit i on s f o r v dd , f cpu , an d t a unle s s ot he rwise sp ecifie d. no tes: 1. data based on characterization results, not te sted in production. 2. hysteresis voltage between s c hm it t trigger s w itching levels. 3. the i io current sunk must alw a y s respect t he absolute maximum rating s pecified in s e c t i o n 1 2 . 2. 2 and the sum of i io (i/o ports and control pi ns) must not exc eed i vs s . 4. to guarantee the reset of the device, a mi nimum pulse has to be applied to the reset pin. all short pulses applied on the re set pin with a duration be low t h( rstl)i n c an be igno red. 5. the res et network (the resistor and tw o capac itors) protects the device again s t parasitic resets, es pecially in noisy en- vironments . 6. data guaranteed by design, not tested in production. symbol parameter c onditions m i n t yp max u nit v hy s schmitt tr igger v o ltage h ysteresis 2) 2.5 v v il input low level voltage 1) 0.16xv dd v v ih input hig h level voltage 1) 0.85xv dd v ol output low level voltage 3) v dd =5v i io =+2ma 0.2 0 .5 v i io driving current on r eset pin 2 ma r on weak pu ll-up equiva lent resistor v dd =5v 20 3 0 120 k ? t w(rstl) out generated reset pulse duration i nternal reset sources 2 0 3 0 4 2 6) s t h( r s t l )i n external reset pulse hold time 4) 2.5 s t g( r s t l )i n filtered glitch duration 5) 200 ns 1 st72324jx st72324kx 137/164 c o n t r o l p i n c har acteristics (c on t?d ) figure 77. reset pi n p r ot ect io n whe n l v d i s enab le d. 1)2)3)4)5)6)7) figure 78. reset pi n pr ote c t i on when lvd is dis a bled. 1)2)3)4) 1. the reset network protects t he dev ice against parasitic resets. 2. the output of the externa l reset circuit m u s t have an open-dr ain output to drive the st7 re set pa d. otherwise the devic e can be damaged when the st7 generates an internal res e t (lvd or watchdog). 3. whatever the reset source is (i nternal or exter nal), the user must ensure that the level on the reset pin can go below the v il max. level spec ified in section 12.10.1 . othe rwise the reset will not be taken into ac count in ternally. 4. because the reset circuit is designed to al low the internal reset to be output in the reset pin, the us er m u st ensure that the current sunk on the reset pin (by an external p u ll-up for ex am ple) is less than the abs olute maximum value specified for i inj(re set) in section 12.2.2 on page 117 . 5. w hen the lvd is enable d , it is mandatory not to co nnect a pull-up resistor. a 10nf p u ll -down capacitor is recommended to filter noise on the reset line. 6. in case a capacitive power supply is used, it is recommended to connect a1m ? pull-down resistor to the reset pin to dis c harge any re sidual voltage induced by this capacitive pow er supply (this will add 5a to the power cons um ption of the m cu). 7. tips when using the lvd: ? 1 . check that all recomm endations related to i ccclk and res et circuit have been applied (see notes above) ? 2 . check that the power supply is properly decoupled (100n f + 10f close to the mc u). refer to an1709. if this cannot be done, it is rec o m m ended to put a 100n f + 1m ? pull-down on the rese t pin. ? 3. the c apacitors c onnected on the res e t pin and als o the power s upply are key to av oiding any s t art-up margin- ality. in most case s, steps 1 and 2 above are sufficient for a robust soluti on. otherwis e : replac e 10nf p u ll-down on the res e t pin with a 5f to 20f capacitor.? 0.0 1 f st72xxx pulse generator filter r on v dd wat c hd og lvd reset in t e rn al re set res e t external recommended 1m ? optional (note 6) 0.01 f v dd 0.01 f e x te rna l res e t circuit user v dd 4.7k ? required recom m ended st72xxx pulse generator filter r on v dd watchdog in t e rn al re set 1 st72324jx st72324kx 138/164 c o n t r o l p i n c har acteristics (c on t?d ) 12. 10 .2 i ccsel /v pp pin su bje c t to g ene ra l o per at ing co ndit i on s f o r v dd , f cpu , an d t a unle s s ot he rwise sp ecifie d. figure 7 9 . two ty pic a l app l ica t ions wit h iccsel/v pp pin 2) n o tes: 1. data based on design simulation and/or technology characteristics, not tested in production. 2. when icc mode is not required by the application iccsel/v pp pin must be tied to v ss . symbol par a meter c onditions m i n m ax unit v il input low level v o ltage 1) v ss 0.2 v v ih input high leve l voltage 1) v dd -0.1 12.6 i l input leakage current v in =v ss 1 a iccsel/v pp st72xxx 10k ? programming tool v pp st72xxx 1 st72324jx st72324kx 139/164 12.11 time r per iph e ral c har acteristics su bje c t to g ene ra l o per at ing co ndit i on s f o r v dd , f osc , an d t a un le ss ot he rw ise sp ec ifie d. re fe r t o i / o por t cha r a c t e r i stics f o r mor e de ta ils o n t he in put / out pu t a l te rn at e fu nct i on cha r act e r i st ics ( o u t - p u t c o m p ar e, in pu t ca ptu r e, e x te rn a l clo ck, pwm ou tp ut ... ). da ta b a sed o n design simu lat i on a nd/ or ch ar acte risat i on r e sult s, no t t e ste d in pr od uctio n . 12. 11 .1 1 6 - b i t t i mer symbol parameter conditions min t yp max u nit t w( ica p )in inp u t capture pulse time 1 t cpu t re s( p w m) pw m resolution time 2t cpu f cpu =8mhz 2 50 ns f ext tim e r ex ternal clock frequency 0 f cpu /4 m h z f pwm pw m repetition rate 0 f cpu /4 m h z res pwm pw m resolution 16 bit 1 st72324jx st72324kx 140/164 12.12 commun ica t ion in ter f ace char acter istics 12. 12 .1 spi - seri al pe ri pher a l i n t e rf ac e su bje c t to gen er al ope ra tin g cond itio ns fo r v dd , f cp u , an d t a un less o t h e r w ise spe c if ied. dat a ba se d on design simu lat i on a nd/ or ch ara c te risat i on r e sult s, no t t e ste d in pr od uctio n . wh en n o co mmun i cat i on is on- goi ng t he da t a out pu t lin e of t h e spi (m osi in m a ste r mod e , miso in sla v e mode) has its alternate function ca pability released. in this case, t he pin status depen ds on the i/o port configuration. refer to i/o port characteristics for more details on the input/output alternate function char- acteristics (ss , sck, mosi, mis o ). figure 8 0 . spi slav e tim i ng diagra m wit h cpha=0 1) no te s : 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol par a meter c ondition s m in m a x u nit f sck 1/t c(sck ) sp i c l oc k frequenc y ma s t e r f cpu =8mhz f cpu /128 0.06 25 f cp u /4 2 mhz slave f cpu =8mhz 0 f cp u /2 4 t r( sck) t f( s c k) sp i c l oc k ris e and fall time see i/o port pin description t su(s s ) ss setup time slave 120 ns t h(ss ) ss hold time slave 120 t w(sck h ) t w(s c kl) sc k hig h and low time ma s t e r slave 100 90 t su( m i ) t su ( s i ) data input s e tup time ma s t e r slave 100 100 t h( mi) t h(si ) data input hold time ma s t e r slave 100 100 t a(s o ) data output ac cess tim e slave 0 120 t dis(so ) data output disable tim e slave 240 t v(so ) data output va lid tim e slave (after enable edge) 90 t h(s o ) data output hold tim e 0 t v(mo ) data output va lid tim e m a s t er (before c apture edge) 0.2 5 t cp u t h (mo) data output hold tim e 0.2 5 ss inp u t sck input cp h a = 0 mos i input miso output cp h a =0 t c(sck ) t w( sckh) t w( sckl) t r(sck) t f(sck) t v(so) t a( so ) t su(si) t h(si) msb o ut ms b i n bi t6 o u t ls b i n ls b o u t se en o t e2 cp o l = 0 cp o l =1 t su(ss ) t h(ss ) t d i s(so) t h(s o ) see no te 2 bit1 in 1 st72324jx st72324kx 141/164 c o mmunication inter f a c e c har acteristics ( c ont ?d) figure 8 1 . spi slav e tim i ng diagra m wit h cpha=1 1) fi gure 8 2 . spi m ast er ti min g di agr a m 1) n o tes: 1. m eas urement points are done at cm os levels: 0.3xv dd and 0.7x v dd . 2. when no communication is on-going the dat a output line of the spi (mosi in mast er mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends of the i/o port configuration. ss in pu t sck input cp ha=1 mosi input mis o output cp ha=1 t w(sc kh) t w(sckl) t r(sck) t f(sck) t a( s o ) t su(si) t h(si) msb o u t bit6 out ls b o u t se e cp ol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c( sck) hz t v(so) ms b i n lsb in bit1 in ss inp u t sck input cpha =0 mosi output miso input cpha =0 cpha =1 cpha =1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in ms b o ut bit6 in bit6 out ls b o ut ls b i n seenote2 seenote2 cpol =0 cpol =1 cpol =0 cpol=1 t r(sck) t f(sck) 1 st72324jx st72324kx 142/164 12.13 10-b it ad c c hara cteristics su bje c t to g ene ra l o per at ing co ndit i on s f o r v dd , f cpu , an d t a unle s s ot he rwise sp ecifie d. n o tes: 1. any add ed external serial resist or w ill downgrade the adc accura cy (es pecially for res i stance greater than 10k ? ). dat a based on characterization resu lts, not te sted in production. 2.for flas h dev ice s : injec t ing negative current on any of the anal og input pins significantly reduces the accuracy of an y conversion being performed on any analog input. analog pins of st72f324 devices can be protected against negativ e injection by adding a schottky diode (pin to ground). injecting negative current on digital input pins degrades a dc accu- racy especially if performed on a pi n close to the analog input pins . any positive injection current within the limits s pecified for i inj(pin) and i inj(pin) in section 12.9 does not affect the adc accuracy. s y mbol par ameter conditions min typ m ax u nit f ad c adc clock frequency 0 .4 2 m h z v ar e f analog reference voltage 0.7* v dd v are f v dd 3.8 v dd v v ai n conversion voltage range 1) v ss a v ar e f i lkg positive input leakage curren t fo r analog input 2) -40c t a + 85c 250 na +85c t a + 125c 1 a r ai n external input im pe dance s ee figure 83 a nd figure 84 2) 3 ) 4) k ? c ai n external ca pacitor on analog input pf f ai n variation freq. of analog input signal hz c adc internal sample and hold capacito r 12 pf t ad c conversion time (sample+hold) f cp u =8m hz , s peed=0 f adc =2mhz 7.5 s t ad c - no of s a m p le capacitor loading cy cles - no. of hold conve r sion c ycles 4 11 1/f adc 1 st72324jx st72324kx 143/164 a dc char acter istics (c on t?d ) figure 8 3 . r ain ma x. vs f adc wi th c ain =0pf 1) fig u re 84 . rec o mmende d c ain & r ain values. 2) figure 8 5 . ty pical a/d con ver ter appl i cat i on no te s : 1. c pa r a si tic represents the capa citance of the pcb (depende nt on sold ering a nd pcb lay out quality) plus the pad ca- pacitance (3pf). a high c para s i t ic value will d o w ngrade conversion accura cy. to rem edy this, f adc should b e reduced. 2. this graph shows that depending on the input signal variation (f ain ), c ain can be increased for stabilization time and decreased to allow the use of a larger serial resistor (r ain) . 0 5 10 15 20 25 30 35 40 45 01 0 3 0 7 0 c par as i t i c (p f ) max. r ai n (kohm) 2 mhz 1 mhz 0.1 1 10 100 1000 0 . 01 0.1 1 10 f ai n (k hz ) max. r ai n (kohm) cain 10 nf cain 22 nf cain 47 nf ainx st72xxx v dd i l 1 a v t 0.6 v v t 0.6v c adc 12pf v ain r ain 10-bit a/d conversion 2k ?( max ) c ain 1 st72324jx st72324kx 144/164 a dc char acter istics (c on t?d ) 12.13 .1 analog po wer supply a nd ref e r e nce pi ns de pen din g on t he mcu pin co unt , t he package may f e a t u r e se par at e v ar ef a nd v ssa an alog power su pply pins. th ese pi n s supp ly po we r to t h e a/ d co nver te r cell a nd f u n c t i on as t h e high and low r e f e r e nc e v o lta g e s fo r t h e co nv er sio n . in so m e package s, v aref an d v ss a pin s ar e no t av aila b l e (r ef er t o se ct ion 2 on p age 8 ). i n th is c a s e t h e an- alog su ppl y a nd r e f e r ence p a d s a r e in te rn ally bon ded t o t h e v dd an d v ss pin s . se pa rat i o n of t h e digi ta l and an alog po we r p i ns al- low boa rd desig ner s t o impr ove a/ d p e r f o rma nce. c o nvers i on accuracy can be im pa ct ed b y vo lta g e dr ops a nd no ise in th e event o f he avily load ed or bad ly decou ple d p o wer su pp ly lines ( s e e section 12. 13 .2 g e n e ra l pcb de sig n gu idelin es ). 1 2 . 1 3 . 2 ge nera l pc b d e s i gn g u idel ines to obt ain b e st re su lts, some g ene ra l de sign and layout r u le s sh ould be fo llowed when de sig n ing th e a pplicat io n pcb t o sh ield the nois e-sens itive, ana log ph ysical int e r f a c e f r om noise -ge ner at ing cm os lo gic sig nals. ? use se par at e dig i t a l and ana log p l ane s. the an- alog g ro und p l ane sh ould b e co nn ecte d to t h e d i git a l gr ou nd pla ne via a single p o in t on t h e pcb. ? filt er power t o th e an alo g po we r pla nes. it is rec- o m me nde d t o con nect ca pa cit o r s, wit h go od high f r equ en cy ch ar acte rist ics, b e t w e en t h e p o wer a n d gr oun d lin es, placing 0. 1 f a nd opt ion a lly, if n e e ded 10p f cap a cito rs as close a s possible to t h e st 7 power su pply pin s an d a 1 t o 10 f ca - p a cit o r close t o th e po we r so ur ce ( s ee fig u r e 86 ). ? the ana log a nd dig i ta l power su pplie s sho u ld b e con n e c t e d in a s t a r ne two r k. do no t us e a re sis- tor , as v aref is us ed a s a r e fer e nc e volt ag e b y t h e a/ d co nver te r and an y re si st an ce w o u l d cau se a v o lt ag e dr o p an d a los s o f acc u r a cy. ? pr ope rly p l ace com pon ent s an d r o u t e t he sig nal t r aces o n t he pcb t o shield t h e a nal og inp u t s . an alog sig n a l s p a t h s sh ould run over th e an alog g r o und p l ane a nd be as sh ort as po ssib le. i s o l at e a n a l og signa ls f r o m digit a l sign als t h a t ma y swit ch wh ile t he a n a l og in put s ar e be ing sam p led by th e a/d co nv er te r. do n o t to g g le d i git a l ou t- pu ts o n th e sa m e i / o po rt as t h e a/d inp u t be in g co nvert e d. figure 8 6 . power supply filte rin g v ss v dd v dd st72x xx v aref v ssa pow e r supply source st 7 dig i tal n oi se filteri n g exte rnal no i s e filte r ing 1 to 10 f 0.1 f 0.1 f 1 st72324jx st72324kx 145/164 10-bit adc ch ara cteris tics (con t?d ) 12.13.3 adc accuracy co ndit i on s: v dd =5v 1) n o tes: 1. ad c accuracy vs. negative injection current: injectin g negativ e curren t m ay reduce the accuracy of the conversion being perform ed on anot her analog input. a n y pos itive injection current w i thin the lim its s pecified for i inj ( pi n) an d i inj (p i n) in section 12.9 does not affec t the adc accur a cy. 2. data based on charac teriza tion results , m onitored in pr oduction to guarantee 99.73% with in max value from -40c to 125c ( 3 dis t ribution limits ). fi gure 8 7 . adc accu rac y ch arac te ri sti c s s y mbol par a meter c onditions flash devices unit typ max 2) |e t | t ota l unadjusted error 1) 46 lsb |e o | o ff set err o r 1) 35 |e g | g ain error 1) 0.5 4.5 |e d | diffe r ential linearity error 1) cp u in run mode @ f adc 2 mhz. 1.5 4.5 |e l | i ntegral linearity error 1) cp u in run mode @ f adc 2 mhz. 1.5 4.5 e o e g 1lsb idea l 1lsb ideal v aref v ssa ? 1024 -- ----- ----- ----- ------ ----- ----- ----- ----- - = v in (l sb ide a l ) (1) example of an a ct u al t r an sf er cu rv e ( 2 ) th e i d e a l tr an sf e r cu r v e ( 3 ) en d po i n t co rr el at i o n li n e e t =t ot al un ad ju st ed er ro r: ma xi mum d e v i a tio n b e t w e e n th e ac t u a l a n d t h e id ea l t r an sf er cu rv es . e o =of f se t e r r o r : de vi ati o n be tw ee n t h e fir st ac tua l tra n s ition an d the f i rs t id e a l on e. e g =g ai n er ror: d evi a t ion betw een t h e l ast i deal tra n s ition an d the l a s t a c tu al on e . e d =diff er en tia l li ne ar ity err o r : max imum d e v ia tio n be tw ee n a c t ua l s t e p s an d th e i d e a l on e. e l =i nt eg ra l li ne ar i t y er ro r: ma xi mu m de vi at i o n be tw ee n an y ac tu al tra n s iti on a n d t h e e n d p o in t co rre la tio n lin e. digita l r e s u lt adc dr 102 3 102 2 102 1 5 4 3 2 1 0 7 6 1 2345 67 10 21 1 02 2 1023 1024 (1) (2) e t e d e l (3 ) v ar e f v ssa 1 st72324jx st72324kx 146/164 13 package charact eristics 13.1 pac kage mec hanical d a ta figure 8 8 . 44-pin thin qua d flat pac kag e figure 89. 32-pin thin quad flat package dim. mm in ch es min t yp max m in typ m ax a 1. 60 0. 063 a1 0 . 05 0 . 1 5 0. 00 2 0 .0 06 a2 1 . 35 1. 40 1 . 4 5 0. 05 3 0 .0 55 0 . 0 5 7 b 0 . 30 0. 37 0 . 4 5 0. 01 2 0 .0 15 0 . 0 1 8 c 0. 0 9 0. 20 0 . 0 04 0 . 000 0. 008 d 12 .00 0.4 7 2 d1 10 .00 0.3 9 4 e 12 .00 0.4 7 2 e1 10 .00 0.3 9 4 e 0. 80 0.0 3 1 0 3. 5 7 0 3. 5 7 l 0 . 45 0. 60 0 . 7 5 0. 01 8 0 .0 24 0 . 0 3 0 l1 1. 00 0.0 3 9 nu mbe r of pins n 44 a a2 a1 b e l1 l h c e e1 d d1 dim. mm inches min t yp max m in typ m ax a 1. 60 0. 063 a1 0 . 05 0 . 1 5 0. 00 2 0 .0 06 a2 1 . 35 1. 40 1 . 4 5 0. 05 3 0 .0 55 0 . 0 5 7 b 0 . 30 0. 37 0 . 4 5 0. 01 2 0 .0 15 0 . 0 1 8 c 0 . 09 0 . 2 0 0. 00 4 0 .0 08 d 9. 00 0.3 5 4 d1 7. 00 0.2 7 6 e 9. 00 0.3 5 4 e1 7. 00 0.2 7 6 e 0. 80 0.0 3 1 0 3. 5 7 0 3. 5 7 l 0 . 45 0. 60 0 . 7 5 0. 01 8 0 .0 24 0 . 0 3 0 l1 1. 00 0.0 3 9 nu mbe r of pins n 32 h c l l1 b e a1 a2 a e e1 d d1 1 st72324jx st72324kx 147/164 packa ge mecha nica l data ( co nt ? d ) fi gure 9 0. 4 2-pi n pla st i c dua l i n -l in e pa ck age, shri nk 60 0- mi l wi dt h - figure 91 . 3 2-pi n pla st i c dua l i n -l in e pa ck age, shri nk 40 0- mi l wi dt h dim. mm in ch es min t yp max m in typ m ax a 5. 08 0. 200 a1 0 . 51 0. 020 a2 3 . 05 3. 81 4 . 5 7 0. 12 0 0 .1 50 0 . 1 8 0 b 0 . 38 0. 46 0 . 5 6 0. 01 5 0 .0 18 0 . 0 2 2 b2 0 . 89 1. 02 1 . 1 4 0. 03 5 0 .0 40 0 . 0 4 5 c 0 . 23 0. 25 0 . 3 8 0. 00 9 0 .0 10 0 . 0 1 5 d 3 6 . 5 8 3 6. 8 3 37 .0 8 1 .4 40 1 . 45 0 1 . 4 6 0 e 15 .2 4 1 6. 00 0. 60 0 0 .6 30 e1 1 2 . 7 0 1 3. 7 2 14 .4 8 0 .5 00 0 . 54 0 0 . 5 7 0 e 1. 78 0.0 7 0 ea 15 .24 0 .6 00 eb 18 .5 4 0 . 7 3 0 ec 1 . 5 2 0. 00 0 0 .0 60 l 2 . 54 3. 30 3 . 5 6 0. 10 0 0 .1 30 0 . 1 4 0 nu mbe r of pins n 42 e e1 ea eb e 0.015 ga ge pl a n e ec eb d e b b2 a2 a1 c l a dim. mm in ch es min t yp max m in typ m ax a 3 . 56 3. 76 5 . 0 8 0. 14 0 0 .1 48 0 . 2 0 0 a1 0 . 51 0. 020 a2 3 . 05 3. 56 4 . 5 7 0. 12 0 0 .1 40 0 . 1 8 0 b 0 . 36 0. 46 0 . 5 8 0. 01 4 0 .0 18 0 . 0 2 3 b1 0 . 76 1. 02 1 . 4 0 0. 03 0 0 .0 40 0 . 0 5 5 c 0 . 20 0. 25 0 . 3 6 0. 00 8 0 .0 10 0 . 0 1 4 d 27 .4 3 2 8. 45 1. 08 0 1 .1 00 1 . 1 2 0 e 9 . 91 10 .41 1 1. 05 0. 39 0 0 .4 10 0 . 4 3 5 e1 7 . 62 8. 89 9 . 4 0 0. 30 0 0 .3 50 0 . 3 7 0 e 1. 78 0.0 7 0 ea 10 .16 0 .4 00 eb 12 .7 0 0. 50 0 ec 1. 40 0. 055 l 2 . 54 3. 05 3 . 8 1 0. 10 0 0 .1 20 0 . 1 5 0 nu mbe r of pins n 32 d b2 b e a a1 a2 l e1 e ec c ea eb 1 st72324jx st72324kx 148/164 13.2 therma l cha racter istic s n o tes: 1. the power diss ipation is obtain ed from the form ula p d =p int +p po rt where p int is the chip internal power (i dd xv dd ) and p po rt is the port power dissipati on determined by the user. 2. the average chip-junction temperatur e can be obtained from the formula t j = t a + p d x rthja. symbol ratings value unit r th ja pac k age thermal resistan ce (junc tion to a m bient) tqfp 44 10x10 tqfp 3 2 7x7 s d ip42 600mil s d ip32 200mil 52 70 55 50 c/ w p d power dissipation 1) 500 mw t jm a x maximum junction tempera t ure 2) 150 c 1 st72324jx st72324kx 149/164 1 3 . 3 so ld eri n g info rm atio n i n or de r to m e et en vir o n m e n t a l r e qu ire m en ts , st of fe rs th ese de vices in ecopack? p a cka ges. t h es e pa ck ag e s h a v e a lea d - f r e e se co nd le ve l in - te rcon nect . th e ca te go ry o f secon d level int e r c on- nect is mar k ed on t h e pa ckag e a nd on th e in ner box l abe l, in co mplia nce wit h jedec sta n d a rd jesd97. t he m a ximum ra ti ng s r e la te d t o so ld er - ing con d it ions ar e also ma rked on t he in ner box la- bel. e c op ack is an st trademark. ecopack? s p e c if icat ion s ar e av aila b l e at www .st . co m . 1 st72324jx st72324kx 150/164 14 st72324 device configuration and ordering information 14.1 flash option bytes the opt ion byte s a llows th e ha rd wa re co nf igur a- tio n of t h e micr ocont r o ller t o be sele cte d . th ey have no ad dre s s i n t h e me mor y map an d can be a c c e s s e d on ly in p r og ra m m i ng m o de ( f o r ex am p l e using a sta n d a rd st7 p r o g r a mmin g to ol) . th e de- f a u l t co nt en t o f th e flash is fixe d to ffh . to p r o - gr am dir e ct ly t h e flash de vices using i c p, flash devices ar e shipp ed t o cust ome r s wit h t h e internal rc clock source. opti on byte 0 opt7= wdg halt wa t c h dog r e set on halt this option bit determines if a reset is generated wh en en te rin g hal t m ode whil e th e wa tchd og is act i ve. 0: no reset gen er at ion when e n t e r i ng halt mod e 1: reset ge ner at ion whe n ent e r ing ha lt mod e opt6= wd g s w hardware or s o ftware w a tchdog this option bit selec t s the watchdog ty pe. 0: har d war e (wa t chd og always ena bled ) 1: so ft war e (wat chdo g to b e en able d by sof t w are ) opt5 = re se rved , must be kept at d e f a u l t value . opt4 :3 = vd [1 :0 ] vo lta ge de te ctio n the s e op tio n bit s ena ble t he vo lta g e de te ct ion block (l vd, and avd) wit h a sele ct ed th re sh old f o r th e lvd a nd avd. ca ution: i f t he mediu m o r low t h re shold s are se- lecte d , th e de te ctio n ma y o c cur ou tside th e speci- fie d ope ra tin g vo lta g e r ang e. be low 3. 8v, d e vice ope ra tio n is n o t g uar an te ed. for det ails on t h e avd and l v d th re sh ol d levels refer to section 12. 4. 1 on p a g e 119 opt2: 1 = re served , must b e kep t at de fa ult valu e. opt0= fm p_ r f l as h m e mo ry re ad -o u t pr ot ec tio n re ad- ou t pr ot ect i on, wh en sele ct ed , p r ovid es a pro t e c tio n ag ainst pro g r a m me mor y co nt ent ex- tr actio n an d aga inst writ e access t o flash me mo- ry. er asing t h e opt ion b y t e s when t h e f m p_r opt ion is se lect ed causes th e wh ole user m e mo ry t o be e r as ed f i rst , a n d th e de vic e ca n be re pr og ra m m ed . re fe r t o sect ion 7. 3. 1 on pag e 37 an d t he st7 flash pro g r a mmin g ref e r ence m anu al f o r mo re det ails. 0: rea d - out pr ot ectio n ena ble d 1: read-out protection disabled static option byte 0 70 sta t ic option b y te 1 70 wdg reserv ed vd reserv ed reserv ed fmp_r pkg1 rstc o sctype oscran g e plloff halt sw 10 1 0 2 10 d e f a u l t 1 11 00 1 1 1 1 1 1 0 1 1 1 1 selected low voltage d e tector vd1 vd0 lvd and a v d o f f 1 1 low es t voltage threshold (v dd ~3v) 1 0 m edium voltage thres hold (v dd ~3.5v) 0 1 h i ghest voltage threshold (v dd ~4v) 0 0 1 st72324jx st72324kx 151/164 st 723 24 d evice co nf ig urati o n and or dering in formation (c on t?d ) opti on byte 1 opt7= pk g1 pin packag e se lectio n bit t h is o p t io n bit se lec t s th e pa cka g e . no te: o n t h e chip , each i/ o po rt h a s 8 pad s. pa ds th at ar e n o t bon de d t o e x t e r n a l pins a r e in inp u t pull- up con f ig ur at ion af t e r r e set . th e co nf igur at ion of th ese pa ds must be ke pt at rese t st at e t o avoid add ed cur r e n t con s u m pt ion . opt6 = rstc r eset clock cycle selection this op tio n bit sele ct s th e nu mbe r o f cpu cycles applied during the r eset ph ase and when exiting h a lt mode. for resonator o scillators , it is adv i sed to s e lect 4096 due to th e long c r ys tal stabilization tim e . 0: reset ph ase wit h 40 96 cpu cycle s 1: reset ph ase wit h 25 6 cpu cycles o p t5 :4 = osc t yp e[1:0] os cillator type t h es e o p t i on b i ts se le ct th e st 7 m a in clo c k so ur ce t y pe. opt3:1 = oscrange[2:0] oscillator range when the resonator oscilla tor type is selected, these option bits s e lect the res o nator oscillator cu rr ent sour ce corr espo ndin g t o t he f r e q u ency ran g e of t h e used re sona to r. o t h e rwise, t h e s e bit s are u sed t o se lect t h e n o rm al ope ra tin g fr eq uen cy r a ng e. opt0 = pll off pll act i vat i on this op tio n b i t ac tiv a t e s the pll which allows mul- tip lica t io n by t w o of t h e main inpu t clock fr eq uen cy. the pll m u st not b e use d with t he int e r nal rc os- c illator. the pll is guar anteed only with an input fr equ en cy bet ween 2 and 4 m hz. 0: pll x2 e nab led 1: pll x2 d i sa bled c aution : th e pl l ca n b e ena bled o n ly if t h e ?osc rang e? (o pt3: 1) bit s a r e co nf igur ed to ? m p - 2~ 4m hz ?. o t h e r wis e, t h e de vice fu nc tio n a li- ty is no t gu ar ant ee d. version s elected package p kg 1 j t q f p44 / sd ip42 1 k t q f p32 / sd ip32 0 clock sour ce oscty p e 10 r e sonator oscillator 0 0 re s e rv e d 0 1 int e rnal rc os cil l a tor 1 0 e x ternal sourc e 1 1 typ. fr eq. r a n ge oscr ange 210 lp 1~2mh z 0 0 0 m p 2~4mh z 0 0 1 m s 4~8mh z 0 1 0 h s 8~16mhz 0 1 1 1 st72324jx st72324kx 152/164 devic e configur ation an d ord e rin g information (con t?d ) 14.2 flash devic e orde ring infor m ation wit h t h e ob jective o f co nt inuo us impr ovem ent , st is d e velo ping ne w st 72f3 2 4 b devices an d is tr an sf er rin g t h e pr od uctio n t o high er capa cit y f abs. re fe r t o th e f o llowing ta bles fo r gu ida n ce on o r de r- ing. st an dard a nd in dust r ial ve rsions f o r n e w d e s i gn s th e st 7 2 f 3 24 b de vice s fr om to t h e sep a r a t e st72 324 b d a t a shee t . for f o r ru nni ng pr od uctio n or de rs se lect t h e devices f r om tab l e 26 1 st72324jx st72324kx 153/164 d evic e configur ation an d ord e rin g information (con t?d ) table 26 . st anda rd and indu str i a l st72 f32 4 flash order code s part numbe r package f lash memor y (kb ytes) temp. range s t 72f324k2b 5 sdip32 8 -10c +85c s t 72f324k4b 5 16 s t 72f324k6b 5 32 s t 72f324j6b5 s dip42 32 s t 72f324k6t5 tqfp32 32 -10c +85c s t 72f324k2t6 8 -40c +85c s t 72f324k4t6 16 s t 72f324k6t6 32 s t 72f324k2t3 8 -40c + 125 c s t 72f324k4t3 16 s t 72f324k6t3 32 s t 72f324j6t5 tqfp44 32 -10c +85c s t 72f324j2t6 8 -40c +85c s t 72f324j4t6 16 s t 72f324j6t6 32 s t 72f324j2 t3 8 -40c + 125 c s t 72f324j4 t3 16 s t 72f324j6 t3 32 1 st72324jx st72324kx 154/164 14. 3 si li co n i d entification the var i ous st72 f324 , st7 2 f3 24b and st 723 24 b de vices ar e iden tif i a b le bo th b y t he last let t e r o f th e tr ace cod e ma rked on th e d e vice package and by t h e last 3 d i git s o f t h e i n t e rna l sa les type pr int e d o n th e box lab e l. table 27. silicon identification (standard and industrial versions) device status fab m emory trace code marked on device internal sales types on box label s t 72f324xxx x current production phoenix 8k to 32k flash ?xxxxx xxxx1? 7 2f324xxxx$x 7 end of prod uction dec. 2005 rousset ? xxxxx xxxxw? 7 2f324xxxx$x 5 s t 72f324bxxx x current production. reco m m ended for new designs rousset 8 k / 16k flash ? xxxxx xxxxb? 7 2f324bxxxx$x4 s t 72324bxxx x c urrent production phoenix 32k rom ? xxxxx xxxxa? 7 2324bxxxx$x1 8k / 16k rom ? xxxxx xxxxb? 7 2324bxxxx$x3 1 st72324jx st72324kx 155/164 14.4 deve lopment tools st microe lect ron i cs of f e r s a ra ng e of h a rd ware and sof t w a r e d e velop m en t t ools f o r th e st 7 m i cr o- c o ntroller family. full details of t ools a v a ilab l e f o r th e st7 f r om t h ir d pa rt y m anu fa ct u r er s ca n be ob- ta in fr om t h e stm i cr oe lec t r oni cs in te rn et s i t e : ? ht tp //: mc u. st. c om . too l s fr om t hese ma nuf act u r e r s includ e c co mpli- er s, emu l at ors an d gan g pr ogr amm e r s . em u l a t or s t w o ty pe s o f em u l at or s a r e av aila ble fr om st fo r th e st72 324 f a m ily: s t 7 d vp3 en tr y-level em ulat or o f fe rs a f l exible and m odu lar d e b ugg ing a nd p r og ra mming so lut i on. sdi p 42 & sdi p 3 2 pr obe s/ ad ap te rs are include d, ot he r pa ckag es nee d a spe c if ic co nne ct ion kit (r ef er t o tab l e 28 ) st 7 e m u 3 hig h - end emu l at or is de live r e d with everyt hin g (p ro bes, teb, a dap te rs et c.) nee ded to st ar t emu l at ing th e st7 232 4 f a m ily. to co nf igur e it t o emu l at e o t h e r st7 sub f amily devices, th e a c t i ve pro b e f o r th e st 7emu3 can be cha n g ed a n d th e st7 e mu3 pr ob e is design ed f o r e a sy in te rcha nge of tebs (t arg e t em ulat ion bo ar d). see ta ble 28 . in -circ u it de bugg ing kit two co nf igur at ion s ar e availa ble f r o m st : stxf521-ind /usb : low-cost in-c ircuit de bu gg in g kit fro m sof t e c m i cro s y s te m s . i n clu des st x- i n dart/ u sb b oar d (usb p o rt ) a n d a specif ic d e mo bo ar d fo r st72 521 ( t q f p64) stxf-in d art fla s h progr ammin g tools st7-stick st7 in-circuit communication kit, a com p let e so ft war e / h a r dwar e package f o r p r o g r a mmin g st7 flash d e vice s. it co nn ects to a host pc pa ralle l por t a nd t o t he t a r g e t bo ar d or socket boa rd via st7 i c c conn ecto r. i cc so cket boa r ds pr ovide an e a sy t o u s e and f l exib le mean s of pr ogr amm i ng st7 fla s h d e vices. t hey can b e con nect e d to any t o o l th at su pp or ts th e s t 7 ic c in te rf ac e, su ch as st 7 emu3, st7-d vp3, inda rt, st7-stick, or ma n y t h ir d- pa r ty de ve lop m en t to ols . ev aluat i on boar d st7232x-eval with i cc connector for programming capabilit y. prov ides direct con n e c t i on t o st7- dvp3 em ulat or . sup p lied wit h d aug ht er boa rd s ( core mod u le ) f o r st7 2 f3 21 , st7 2 f3 24 & st 72f 521 (t he st7 2 f3 21 & st72 f324 ch ips a r e n o t in clu ded ) table 28 . stmic r oelec t ro nic s deve lo pment t ools n o t e 1: ad d su ffix /eu , /u k, /us fo r t h e p o w er s u p p ly o f y o u r re g i on . supported pr oducts emulation p rogramming st7 dvp3 s e r i es s t 7 emu 3 series icc socket board emulator connection kit e mulator active probe & t.e.b. s t 72324bj, s t 72f324j, s t 72f324bj st7m dt20-dvp 3 s t 7mdt20-t44/ dvp s t 7mdt20j- emu 3 st7mdt20j-teb st7sb 20j /xx 1 s t 72324bk , s t 72f324k, s t 72f324bk st7m dt20-dvp 3 s t 7mdt20-t32/ dvp 1 st72324jx st72324kx 156/164 14. 4. 1 so cke t a nd emul at or ada p te r in forma ti on f o r in fo rm at ion on th e ty pe of s o c k e t tha t is su p - p lie d w i th th e em u l at or , r e f e r to th e su gg e s te d list of sockets in t ab l e 29 . no te: bef o r e de sig n in g t he b oar d la yo ut , it is re c- omme nd ed to check t he over all d i men s io ns of t h e so cket as t h e y may be gr ea te r th an t he dim en- s i on s of th e de vic e . f o r f o o tp r in t an d ot he r m e ch an ica l in fo rm a tio n abo ut th ese socket s a n d ada pt er s, re fe r t o t h e manufacturer?s datas heet (www.yamaichi.de for tqfp4 4 1 0 x 10 an d www. iro n woo dele c t r on- ics. co m fo r tqf p 32 7 x 7 ) . tabl e 29 . sugg est ed li st of sock et t y pes device socket (supplied with st7md t20 j-emu 3 ) emulator adapter (supplied w i th s t 7mdt20j-em u3) tqfp 32 7 x 7 i ronw ood sf-q fe32sa-l-01 ironw o o d sk-uga 0 6/32a-0 1 tq fp44 10 x10 y a maichi ic 14 9-044-*52-*5 y a maichi icp - 044-5 1 st72324jx st72324kx 157/164 14.5 st7 applic ation n o tes table 30 . st7 applica t ion no te s identifica t i on des crip t ion a pplica t ion exam p les a n 1658 ser ial numbe ring impleme n tatio n a n1720 m anaging the r ead-o ut pr otection in flash micr ocontr ollers an 1755 a hig h r esolution/precisio n ther mome ter u sing st7 and ne555 e x ample drivers a n 969 sci c o mm unica tion betw een st7 and pc a n 970 spi c o mm unica tion betw een st7 and eepr om a n 972 st7 softw are spi master co mmunication a n 973 sci s o ftwar e co mmun i cation with a pc usin g st72251 16-bit timer a n 974 rea l time c l ock with st7 tim e r o u tput c o mpar e a n 976 driving a buzze r thro ugh st7 timer pwm fun c tion a n 979 driving an an alog keybo ard w i th the st7 ad c a n 980 st7 keypad deco din g tec hniq u es, impleme n ting w ake-u p on key stroke a n1041 using st7 p w m sig nal t o g e nerate analo g o utput (sinuso?d) a n1044 m ultiple inte rrupt source s m anagem ent fo r st7 mcus a n 1046 uar t em ulatio n so ftware a n 1047 m a naging reception error s w i th the st7 sci pe riphe r als a n1048 st7 softw are lcd dr iver a n1078 pw m duty c y cle switch implem entin g tru e 0% & 100% duty cycle a n 1445 em ulated 16 bit slav e spi a n 1504 star ting a pwm signal dire ctly at hig h le vel us ing the st7 16-bit tim e r g e neral purpo s e a n 1476 low c o st p o we r sup p ly fo r ho me applia nces a n 1709 em c de sign for st mic r ocon trollers a n 1752 st72324 quick re ference note p roduct evalua t ion a n 910 per forman ce b e nchma r king a n 990 st7 benefits v ersus indu stry s t andard a n 1150 ben chmark st72 vs p c 16 a n1151 per forman ce c o mpar ison betw een st72254 & pc16f876 a n1278 lin (local inte rconne ct netw ork) s o lutio ns p r oduct migration a n 1131 m i gra t ing applications from st72511/311/214/124 to st72521/321/324 a n 2197 g uidelines for mig ratin g s t 72 f324 & s t 72f 321 applicatio ns to st72f324b, st72f321b or st72f325 p r oduct optimization a n 982 using st7 w i th cera mic reso nator a n1014 ho w to m i nimize the st7 p o we r co nsumption a n1015 so ftware techn ique s for improv ing microc o ntroller em c per forman ce a n 1070 st7 checks u m self-ch eckin g c apabil i ty a n 1181 elec trostatic discha rge sensitive meas uremen t a n 1502 em ulated data eeprom w i th st7 hd flash m e mor y a n 1530 acc urate timeba se for low-cos t st7 applications w i th internal rc oscilla- tor a n 1636 und erstanding and minimizin g a dc co nversion erro rs p r ogra mming and to ols 1 st72324jx st72324kx 158/164 a n 978 st7 vis ual de velop softw are k ey de bugging feature s an 983 key featur es o f the cosm ic st7 c - co mpile r pac kage a n 985 exe cutin g co de in st7 ram a n 986 using the indirect addres sing mo de with st7 a n 987 st7 serial tes t con t roller prog ramming a n 988 star ting with st7 ass embly tool chain a n 989 g e tting starte d w i th the s t 7 hiware c toolcha in a n 1039 st7 math utility r o utines a n 1064 w r iting optimize d hiwar e c langua ge fo r s t 7 a n1106 tran slating as sembly code from hc 0 5 to st7 a n 1446 using the st72521 em ulator to d ebug a s t 7 2324 targe t application a n 1478 po rting an st7 panta project to c o dew a rrior ide a n1575 o n-bo ard p rogr amming metho ds fo r xflas h and hdflas h st7 mcus a n1576 in-ap p lication prog ramm ing (iap) dr ivers for st7 hdflash or xflash mcus a n1635 st7 custom e r rom code releas e inform atio n a n 1754 data log g in g pr ogra m fo r testing st7 a pplica t ions via icc a n 1796 field u p dates for flash b ased st7 app lications using a pc com m p o rt s ystem optimiza t i on a n1711 so ftware techn ique s for co mpensa ting st7 a dc e rrors table 30 . st7 applica t ion no te s identifica t i on des crip t ion 1 st72324jx st72324kx 159/164 15 known limitations 15. 1 all devi ces 15. 1. 1 ext e rn al rc o p ti on the exte rn al rc clo c k so ur ce o p t i on de scr i bed in pr evious dat ashe et r e visi ons is no lo nge r supp or t- ed an d ha s be en r e move d fr om t h is sp ecificat ion . 15. 1. 2 css fu nct i o n the clock securit y syst em f unct i on ha s bee n r e - moved f r om th e da ta sh eet . 15.1.3 saf e conne ction of osc1/osc2 pins the osc1 an d/ or osc2 pin s must n o t be le ft un- c o nnec t ed otherwis e the st7 main oscillator may st ar t and , in t h is conf igu r a t io n, co uld gen er at e an f os c clock frequency in excess of t h e allowed maximum (>16m hz. ) , put t i ng t h e st 7 in an un- sa fe /u nd ef ined st at e. ref e r to sectio n 6 . 2 on p age 24 . 15. 1. 4 unex pec t e d re set f e t c h if an int e rr upt re que st occu rs wh ile a ?po p cc? in- st r u ctio n is execut ed, th e in te rr up t co nt ro ller do es not r e cog n ise t h e sou r ce o f th e in t e rr up t and , by def au lt, p a sse s t h e reset ve ct or ad dre s s t o t h e cp u . wo rkar ound to solve this iss u e, a ?pop cc ? instruction must a lwa ys be p r ec ed ed b y a ?si m ? in str u c t io n. 15. 1. 5 cl ear ing act iv e i n te rrup t s ou ts ide in ter r upt r outine wh en an active int e r r u p t re que st o c cu rs at t h e sa me tim e as t he re lat e d f l ag is b e ing clea re d, an unwan te d re se t ma y occur . no te: clearing the related in terrupt mask w ill not gen er at e an un want ed r e set co ncurr e nt int e rr upt c onte x t t h e sy mp to m do es n o t oc cu r wh en the int e r r u p t s ar e han dled n o r m ally, i. e. wh en: ? the int e rr up t f l ag is cle a re d with i n its own int e r - rup t r out ine ? the int e rr up t f l ag is cle a re d with i n any int e r r u p t rou t ine ? the int e rr up t f l ag is cle a re d in an y pa rt of t h e c o de while this interrupt is disabled if t h e s e cond itio ns ar e not me t, t h e sym p t o m can be a v o i ded by imple m en tin g t he f o llo wing se- que nce: pe rf or m si m an d ri m op era t ion b e f o r e an d a f t e r re se tt ing a n acti ve in te rr upt re que st . exam ple: sim re se t int er r upt fla g ri m ne ste d in ter r upt c ont ext : the symp to m d oes not o c cur whe n t h e in te rr upt s a r e ha nd le d no rm a lly, i.e . wh en: ? the in te rr up t f l ag is clea re d wi th in its own int e r - ru pt ro u t in e ? the in te rr up t f l ag is clea re d wi th in any int e r r u p t r o u t in e with h i ghe r or i den tical pr ior i t y level ? the in te rr up t f l ag is clea re d in an y pa rt of t h e code while this interrupt is disabled if t h e s e cond itio ns ar e n o t me t, t h e symp to m can be a v o i ded by imple m en tin g t he f o llo win g se- que nce: pu sh c c sim re se t int er r upt fla g pop c c 15. 1. 6 ext e rn al i n t e rru pt mi ss ed to avoid a n y risk o f ge ne rat i n g a par asit ic in te r- rup t , t he e d g e de te ct or is a u t o ma tica lly d i sa bled fo r on e clo c k cycle d u rin g an a c ce ss to eit her ddr and or. an y inpu t sign al e dge du ring t h is per iod w ill not be detected and will not generat e an inter- rup t . this case can typically oc cu r if t he ap plicat ion r e - fr eshe s t he po rt co nf igur at ion r e g i st er s a t int e r vals dur ing r unt ime . wor kar ound the wo rkar ou nd is b a sed on so ft war e che c king t h e leve l on t h e in te rr u p t p i n be fo re an d a fte r wr it- ing to t h e pxor or pxddr r e g i st er s. if th ere is a level ch ang e ( d e pen din g o n th e se nsitivit y pr o- g r am m e d fo r th is p i n) th e in te rr up t r o ut ine is in - vo ke d using th e ca ll instr u ct ion wit h t h re e ext r a push inst ru ct ion s be fo re execut ing t he int e r r u p t r o ut ine ( t his is to m a k e t h e c a ll c o mpatible w i th the iret in str u ctio n at t h e en d of t h e int e r r u p t ser vice rou t in e) . bu t det ect i on of t he l e vel cha nge do es ensu r e th at edg e occurs du rin g t he crit ical 1 cycle dur at ion and th e int e r r u p t h a s bee n misse d . this may lead to occu rr ence o f sa me in te rr upt t w ice (on e h a rd wa re and a not he r with sof t w are ca ll). 1 st72324jx st72324kx 160/164 known lim i tations (cont ?d) to avoid t h is, a semap h o r e is set t o '1' b e f o re ch eckin g t h e level cha nge . t he sem aph or e is ch ang ed to level '0 ' insid e t he i n t e rr up t r o u t in e. wh en a level cha n g e is d e t e ct ed, t h e sema ph ore st at us i s ch ecke d and if it is '1 ' t h is mean s t hat t h e last in te rr upt has be en missed. i n th is case, th e in- te rr upt ro ut ine is invok ed with the c a ll ins t ruction. the r e is ano th er p o ssib le ca s e , that is, if writing to p x or or p x dd r is done with global interrupts dis - a b l ed ( i n t e r r u p t ma sk b i t se t) . i n th is ca se , th e se map hor e is ch ang ed t o ' 1 ' whe n th e le ve l ch ang e is de te ct ed . det e ct ing a misse d int e r r up t is d o n e af te r th e g l ob al in te rr up ts a r e en a b le d ( i nt er - ru pt ma sk bit r e set ) and b y checking t he st a t u s of th e se map hor e. i f it is '1' th is me ans th at t h e last int e r r up t was misse d and t h e int e r r up t r out ine i s in- v o k e d w i th the call instruc t ion. to im p l em e n t th e wo rka r ou n d , th e fo llow i ng so ft - w a r e se qu en ce is to b e f o llowed for w r iting into the pxo r / p xddr reg i st e r s. th e exa m ple is f o r po rt p f 1 with falling edge interrup t sensitiv ity. the soft- wa re seq uen ce is g i ve n fo r bo th cases ( g lo bal in- te rr upt disab l ed/ en able d ) . ca se 1 : writing to pxor or pxd dr with global in- te rr upt s en able d : ld a, #0 1 ld sem a , a ; set t h e sem aph or e to ' 1 ' ld a,pfdr a nd a , #02 ld x, a ; st ore th e le ve l bef or e writ ing to p x or /pxd dr ld a, #$ 90 ld pfddr,a ; write to p f d d r ld a, #$ ff l d pfor ,a ; w r ite t o pfor ld a,pfdr a nd a , #0 2 l d y,a ; st or e th e le vel after writing to p xor /pxd dr ld a, x ; check f o r fa lling ed ge cp a, #0 2 jrne out tnz y jrne out ld a, sema ; ch eck th e sem aph or e st at us if edg e is d e t e cte d c p a, #0 1 jrne out c a ll call_routine; c a ll th e int e r r up t r out ine out:l d a, #0 0 ld sem a , a .call_routine ; entr y to call_routine pu s h a pu s h x p u sh cc . e x t 1 _ r t ; e n t r y to in te rr up t ro ut ine ld a, #0 0 ld sem a , a iret ca se 2: w r iting to px or or pxd dr with global in- te rr upt s disab led: s i m ; se t th e int e r r u p t m a sk ld a,pfdr and a, #$ 02 l d x,a ; st or e t h e le vel before writing to p xor/px ddr ld a, #$ 90 ld pfddr ,a ; write into pfdd r ld a, #$ ff l d pfor ,a ; w r ite t o pfor ld a,pfdr and a, #$ 02 l d y,a ; st or e th e le vel after writing to p xor/px ddr ld a, x ; check f o r fa lling ed ge cp a, #$ 02 jrne out tnz y jrne out ld a, #$ 01 ld sem a , a ; se t t h e sema ph ore t o '1 ' if ed ge is det ect e d r im ; re se t t h e in te rr up t ma sk ld a, sema ; check t h e sem aph or e st at us cp a,# $01 jrne out c a ll call_routine; c a ll th e int e r r up t r out ine ri m out: ri m 1 st72324jx st72324kx 161/164 j p while_loop .call_routine ; entr y to call_routine pu s h a pu s h x p u sh cc . e x t1 _ r t ; e n t r y to in te rr up t ro ut ine ld a, #$ 00 ld sem a , a iret 15. 1. 7 16 -b it t i me r pwm mod e i n pwm m o de , the f i rs t pw m pu lse is m i sse d af te r wr it ing t he value ff fch in th e oc1r r e g i st er ( o c 1 h r , o c 1 l r ). it lea d s to e i th er fu ll o r no pwm dur ing a per iod , de pen ding on t h e ol vl1 and olvl 2 se tt ing s . 15. 1. 8 sci wrong bre ak dura t i on de scr ipt i on a sin g le br ea k ch ar ac te r is s e n t by se tt ing a n d re - setting the sbk bit in th e s c icr 2 register. in s o me cases, the break cha r a c t e r may have a lo ng- e r du r a t i on th a n ex pe cte d : - 2 0 bit s in st ea d of 1 0 bit s if m = 0 - 2 2 bit s in st ea d of 1 1 bit s if m = 1 . in the same w a y, as lo ng as the sbk bit is set, br eak cha r a c t e r s ar e se nt t o t h e tdo pin. this may lead to g ene ra te o n e b r e a k m o re th an exp e ct- ed. occurrence the occu rr en ce of t h e pr oble m is r and om and pr o- por tio n a l t o t he ba udr at e. wit h a t r a n smit f r e que n- cy o f 1 9 2 00 bau d ( f cpu=8 m hz and sci - brr=0xc9 ), t he wr on g br ea k dur at ion occurr en ce is ar ou nd 1%. wor kar ound if t h is wr ong d u ra t i on is not c o mpliant with the co mmun i ca tio n pr ot ocol in t h e app lica t ion, so ft - wa re can re que st t h a t an i d le line be ge ner at ed bef or e t he br ea k char act e r. in t h is case, t h e b r e a k dur at ion i s al wa ys corr ect assu ming th e ap plica- tio n is n o t d o in g anyt h in g bet wee n th e idle a nd t h e bre a k. this can b e e n sur ed b y te mpo r ar ily disa- bling interrupts. the e x a c t se que nce is: - disa ble int e r r u p t s - re se t a nd set te ( i dl e r equ est) - set a nd reset sbk (br eak requ est) - r e - e n a b le in te rr up ts 15.2 flash devices only 15. 2. 1 i n te rna l rc op erat i o n in st72f 324 j and st72 f324 k de vices, t h e in te r- nal r c os cillator is not su pported if the lvd is dis- able d . 1 st72324jx st72324kx 162/164 16 important notes on st72f324b flash device s: wit h t h e ob jective o f co nt inuo us impr ovem ent , st has de ve lope d ne w st7 2 f3 24b de vice s. the s e devices ar e fu lly com pat ible wit h a ll ro m fe at ur es and pro v ide a n impr oved price/ p e rf or ma nce ra tio co mpa r e d to t h e st7 2 f3 24 f l ash de vices. a sum m ar y o f t h e t e chn i cal impr ovem ent s is given belo w . re fe r to sepa ra te st72 32 4b d a t a shee t fo r th e o r - der ing in fo rma tio n an d full specifications . 16.1 res e t pin logic leve ls in st72 f324 b flash d e vices, t h e v ih /v il levels for th e r e set pin ar e t h e same as specif ied fo r ro m devices 16. 2 wake -up fr om act i ve hal t mode us in g ext ern a l i nt e rru pts in st72 f324 b flash d e vices, a n y ext e r nal in te r- ru pt t hat cap able of waking -u p t h e mcu f r o m halt mod e ca n also wake- up t he mcu fr om active halt mod e . con s e que nt ly n o t e 1 belo w ta ble 8 on pag e 36 d oes not app ly t o ?b? d e vices. 16. 3 pll ji t t er in st72 f324 b flash d e vices, pl l clock a c cu racy is impr oved a nd th e jitt e r is th e sa me as spe c if ied fo r rom de vices 16.4 act i v e ha lt powe r cons umpt io n in st7 2 f3 24b flash dev ices, t h e po we r con- su mpt i on in act i ve ha lt mo de is sp ecifie d as 230 a max. see t able 1 2. 5. 1 on p age 1 2 0 fo r te st co ndit i on s. 16. 5 ti mer a reg i s t e r s i n st 72 f 3 2 4 b f l as h d e vice s, all t i m e r a re gis t e r s are pr esent a nd t h e i r f u n c t i o nalit y is t h e same as describ ed fo r ro m d e vice s in th e st7 232 4b d a - ta sh eet . 1 st72324jx st72324kx 163/164 17 revision history tabl e 31 . rev i s i o n hi st ory date revision description of changes 0 5 -may-2 004 2.0 merged st72f324 flash with st72324b rom datasheet. vt por max m o d i fied in section 12.4 on page 119 added figure 78 on page 137 modified v aref mi n in ?10-bit adc cha racteristics ? on page 142 modi fi ed i inj for pb0 in section 12.9 added ?clearing active interrupts out side interrupt routine ? on page 159 modified ?32k rom devices only? on page 164 30-mar-2005 3 removed cloc k security system (css) throughout document added notes on st72f324b 8k/16k flash devices in table 1 and table 27 correc ted m c o de scription in table 1 and s e c t ion 10.2 modified vtpor in sectio n 12.4 on page 119 static current cons um ptio n modified in sec t ion 12.9 on page 133 updated footnote and figure 77 and figure 78 on page 137 modified solderin g information in s e c t ion 13.3 updated s e c t ion 14 on page 150 added table 27 modified figure 7 and note 4 in ?flash prog ram mem o ry ? on page 17 added limitation on icc entry mode with 39 pulse s to ?kno wn lim i tations ? on p age 159 added section 16 on page 162 for st72f324b 8k/16k flash devic es modified ?internal sales ty pes on box label? in table 29 08-nov-2005 4 removed inform ation on st72f324b and ro m d e vic e s (now in s eparate datasheet) 04-apr-2008 5 changed status to ?n ot for new design? added ?ex t ernal interrupt missed? in ?kn o wn lim i tations? on page 159 removed inform ation on automotive ve rsions (now in s eparate datasheet) 1 st72324jx st72324kx 164/164 pl ea se r e a d c a r e fu ll y: inf o r m a ti o n in th is d o c u me nt is pr ov id ed s o le ly in c o n n e c t ion with st p r od u c ts . stmicr o e le c tr on ic s nv a n d i ts su bs id iar ie s ( ? st ? ) re se rve t h e right to make ch an ge s, co rre ct ion s , mod ific at io ns or i m pro v e m en ts , to thi s d o c u me nt , an d th e p ro d u c t s a n d se rv ice s d e s c rib ed he r ei n at an y time , with ou t n o tic e. al l st pr od uc ts ar e s o l d p u r s u a n t t o st?s te rms an d co nd itio ns o f s a l e . pu rc ha se rs ar e s o l e ly re sp on si bl e fo r t h e ch oi ce , se le ct ion an d us e o f th e s t pr od uc ts an d s e r v ic e s d e s c r i be d h e r ei n, an d s t as su m e s n o l i a b i li t y wh at so ev er re la t i n g t o t h e cho i c e , s e l e c t io n or us e of t h e s t pr od uc t s an d se r v i c e s de sc ri b e d h e r e i n . no li ce ns e, ex pr es s or imp lie d, by es to pp el or o t he rw is e, to an y in tel l ec tu al pr op er ty rig h t s i s g r a n t e d u n d e r th is do cu men t. i f an y pa rt of t h i s do cu men t r e fe rs to a n y th ird p a r t y pr od uc ts or s e r v ic es it sh a ll n o t be d e e m ed a lic en s e g ra n t by s t fo r t h e us e of su ch th ir d p a r t y pr od uc ts or se rv ic es , o r an y int e l l ec tu al pr op er ty co nt ain e d t h e r e i n or c o n s i d e r ed a s a w a rr an ty c o v e r i ng t h e u s e in a n y ma nn er w h a t s o e v e r o f such t h ir d p a r t y pr od uc ts or s e r v ic es o r a n y i n te l l e c t u al p r op er ty co nt ai ne d t h e r e i n. u n le ss ot her wis e se t fo rth in s t ?s t e rms and c ondition s of sale st dis c la ims any exp res s or imp l ied wa rrant y wit h r esp ect to th e u se and /or s a le of st p roducts includ ing with out limitat i on imp l ied wa rrant ies of merc hant ability , f i t nes s for a part icul a r pur p ose (a nd th eir equ i v a le nts u nder the l a ws o f any j urisdict i o n), or inf rin geme nt of a ny pat e nt , co pyr igh t or ot her inte lle ctu al pro per ty right . u n le ss ex pre ssl y app rove d in wr it in g by an au thor iz ed st r epr ese ntat iv e, st pr oduc ts are not r e comm e nde d, auth orized or warra nte d for u se in mi litar y , air craf t, spa ce, life s a ving , or life s u st aining ap plica tions, n or in p rodu cts or s yst ems where fail ure or mal f un ction may r esul t in p e rs onal inju ry, de ath , or s eve re p rop ert y or env i ronme n tal da mage. s t p rodu cts which a r e not s pec if ie d as "a utomo t ive grade" ma y onl y be us ed in auto m otive a ppl ic ations a t use r?s own risk. r esal e of s t p r o duct s wi t h p r ovi s i o ns d i f f er e nt f r o m t h e s t at eme nt s an d/ o r techni c al f eat ur es se t f or t h i n t hi s documen t sh al l i mmed i a t el y vo id a ny wa rr anty gr a nt ed by st fo r t h e s t pr o duct or se r vi ce de scri bed her e i n an d s hal l n ot c r e at e o r ext e nd in an y m anner wh at s oev er , a n y liabil ity o f st. s t an d the st l ogo ar e tr ade marks or re gi st e r e d tr a dem ar ks of st i n va r i o us c ount r ies. i n fo rm at io n i n t h i s d o c u me nt su pe rs ed es a n d re pl ac es al l i n f o rma t io n p r e v i o u s l y s u p p l i e d . t he s t l ogo is a r egi s t er ed t r adema r k o f s t mi cr o el ect r o ni cs. a l l other n ame s a r e t h e pr oper t y of t hei r re specti v e own er s . ? 20 08 s t mi cro e l e c t ro ni cs - al l r i gh ts re se rv ed stmi c ro el ec t r o n i c s gr ou p of co mpa n i e s au st ra lia - b e lgi u m - b r a z il - ca na da - chin a - cz ec h re pu bl ic - f i n l an d - f r a n c e - ge rma n y - ho ng k o n g - i n d i a - i s ra e l - ita l y - ja pa n - malaysia - ma lt a - mor occo - singapor e - spa i n - sw eden - swi t zer l a nd - uni t ed k i ngd om - uni t ed stat es of a m er i ca ww w.st.c om |
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